Senior Principal Engineer, Hardware Application Engineering — Board & System Design

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

As Senior Principal Engineer for Board & System Hardware Design you will be the senior technical authority guiding customer hardware design-in on Marvells Ethernet Switch and UALink platforms and a key technical bridge between Marvells silicon teams internal hardware engineering and the field. Your primary mission is to ensure that customers next-generation switches AI fabric platforms and networking systems are designed right the first time performant manufacturable reliable and ready for high-volume production.

This is a deep individual contributor role with a strong system-design and productization focus. You will spend most of your time reviewing and shaping customer hardware designs covering board architecture PCB stack-up and material selection power architecture thermal design mechanical integration and reliability and retain full hands-on capability across the entire design lifecycle from architecture through schematic layout guidance and bring-up. You will also play a central role in defining and supporting reference designs for new silicon and serving as a trusted technical educator to both customers and internal teams. You will be a key technical voice in Marvells evolution toward 224G and 448G SerDes-class systems and the emerging open AI fabric standards.

• Serve as the senior technical advisor to customer hardware teams designing platforms around Marvells Ethernet switches and UALink silicon from early architecture through production ramp.

• Lead design-in reviews of customer schematics PCB stack-ups and overall system architectures identifying risks early and guiding customers to best-in-class implementations.

• Define develop and support reference designs for new Marvell silicon partnering with silicon packaging and internal HW engineering teams from early product definition through customer release.

• Work closely with Marvells internal hardware engineering and silicon teams as a feedback channel from the field influencing silicon I/O package power and reference design choices based on real customer deployment learnings.

• Drive PCB stack-up strategy and material selection (low-loss laminates copper roughness glass weave via construction) to meet high-speed performance and cost targets.

• Own architecture schematic layout guidance and bring-up of Marvell reference and evaluation platforms applying full lifecycle hands-on expertise where needed.

• Guide customers on power delivery architecture including PDN design multi-rail sequencing decoupling strategy and tolerance analysis for high-current ASICs.

• Advise on thermal design mechanical integration and cooling strategies (air liquid immersion) to meet performance and reliability targets in real deployments.

• Provide guidance on signal and power integrity reviewing customer SI/PI simulations and contributing simulations directly when the project requires it.

• Drive design for reliability manufacturability and testability ensuring smooth transitions to production at ODM/CM partners.

• Develop and deliver technical training to customers and internal Marvell teams covering Marvell silicon reference designs high-speed design best practices and productization methodologies.

• Provide technical leadership on 112G and 224G PAM4 SerDes designs today and help shape Marvells hardware approach for next-generation 448G systems.

• Lead hardware bring-up support root-cause debug and issue resolution during customer lab phases and early production.

• Partner closely with Marvell Silicon Design Packaging SI/PI Software and Operations teams to deliver fully integrated solutions.

• Contribute to product definition and roadmap planning by bringing real-world customer feedback into architecture and marketing discussions.

• Represent Marvells hardware expertise in customer briefings executive reviews and industry technical forums.

What Were Looking For

• PhD Masters or Bachelors degree in Electrical Engineering Computer Engineering or a related field.

• 15 years of experience in hardware design development and validation of high-speed networking or compute systems.

• 7 years of dedicated experience in board and system design for high-speed platforms involving modern SerDes (25G NRZ through 112G/224G PAM4).

• Proven full-lifecycle ownership of complex high-speed boards: architecture schematic layout guidance and bring-up.

• Demonstrated experience defining and delivering reference designs that enabled customer or internal platform adoption.

• Strong expertise in PCB stack-up design and material selection for high-speed high-layer-count boards.

• Deep experience with power architecture for high-current ASICs including PDN design sequencing decoupling and tolerance analysis.

• Solid background in thermal design and mechanical integration for high-power network and AI systems.

• Working knowledge of SI/PI principles with the ability to review customer simulations and run targeted simulations independently when needed.

• Hands-on experience with hardware bring-up lab debug and root-cause analysis using industry-standard lab equipment.

• Deep understanding of high-speed interfaces: Ethernet PCIe DDR advanced SerDes and modern power delivery architectures.

• Strong grasp of design for reliability manufacturability and testability across the product lifecycle.

• Customer-facing experience supporting complex technical engagements and resolving real-world deployment issues.

• Proven ability to develop and deliver technical training content to engineering audiences.

• Excellent communication skills with the ability to influence senior customer engineering teams and collaborate across disciplines and geographies.

Preferred

• Direct experience with Ethernet switch platforms (any tier) and/or emerging open AI fabric standards and architectures.

• Experience designing or reviewing platforms targeting megascale data center deployments.

• Background in reference platform design and customer enablement for silicon-based solutions.

• Familiarity with ODM/CM manufacturing flows including DFM/DFT qualification and reliability testing.

• Experience with advanced cooling approaches (liquid immersion) for high-power AI/networking platforms.

• EDA tool fluency in either Cadence (Allegro/Sigrity) or Mentor/Siemens (Xpedition/HyperLynx) ecosystems tool-agnostic candidates with deep expertise welcome.

• Track record of influencing silicon and platform roadmaps based on customer and field insights.

Leadership & Impact:

As a senior technical leader within the Customer Solutions Group you will:

• Set the technical bar for board and system hardware design quality across Marvells most strategic customer engagements.

• Serve as a key technical interface between customers Marvell silicon teams and internal hardware engineering accelerating learning in both directions.

• Mentor engineers across the team and lead training for customers and internal stakeholders raising collective expertise in system design productization and customer enablement.

• Shape the direction of Marvells customer-facing hardware solutions and influence next-generation product evolution.

• Act as a technical ambassador representing Marvells hardware capabilities to top-tier customers and partners.

• Travel as needed to customer sites ODMs and labs typically project-driven rather than continuous.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.