Principal Physical Design Engineer, STA

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Location: San Jose CA

Position Type: Full-Time

Broadcoms ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the worlds most innovative technology companiesspanning hyper-scale cloud providers AI pioneers and tier-1 networking infrastructure leadersto co-design and manufacture complex custom ASICs that power the modern digital backbone.

The Physical Design team within APD is the world-class execution engine behind the industrys most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise advanced IP cutting-edge physical design methodologies in 3nm/2nm nodes and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth transform ultra-complex architectures into fully realized high-yielding first-pass silicon success.

• Pioneering First-Pass Silicon in 3nm/2nm: Our team consistently pushes the boundary of physics taking the largest and most complex die sizes from floorplan to tapeout on leading-edge foundry nodes (N7 N5 N3 and N2).
• Record-Breaking Scale & Complexity: We regularly execute full-chip physical implementation for ultra-large-scale ASICs exceeding tens of billions of transistors multi-gigahertz clock frequencies and dense multi-die 2.5D/3D integration (CoWoS HBM3/4 chiplet architectures).
• Methodology & Flow Leadership: We develop and maintain cutting-edge in-house (AI Driven) automation and methodology across different EDA tools setting the benchmark for signoff quality and turn-around-time (TAT).
  

At Broadcom we shape the future of global technology by delivering world-class custom silicon and infrastructure solutions that power the largest hyperscale data centers and advanced AI platforms on earth. The ASIC Products Division is seeking a talented Full-Chip Static Timing Analysis (STA) Engineer to join our elite engineering team.

In this highly visible role you will be responsible for ensuring that our high-performance next-generation ASICs meet their aggressive performance targets and tight timing requirements across all operating conditions. This position is tailored for engineers eager to leverage next-generation EDA flows employing AI-driven automation and machine learning to maximize compute infrastructure efficiency and accelerate timing closure. If you thrive on solving complex timing puzzles at advanced sub-nodes managing multi-mode multi-corner (MMMC) scenarios at massive scale and pioneering AI-assisted methodologies this is where you belong.

• Full-Chip Timing Sign-off & Constraints: Own final timing closure across PVT corners authoring and maintaining SDC for functional and test modes.
• AI & Infrastructure Optimization: Deploy AI/ML automation within STA flows to minimize execution runtime maximize shared server/infrastructure efficiency and implement ML-based corner reduction while ensuring full physical coverage.
• Triaging & Marginalities: Utilize automated workflows and data-mining to rapidly triage violations isolate root causes and systematically eliminate timing and design marginalities across complex clock networks and multi-die boundaries.
• Methodology ECOs & Collaboration: Leverage advanced OCV/SI/IR-drop concepts drive timing ECOs and partner cross-functionally with RTL Physical Design and DFT teams to optimize PPA.
  

• Education & Experience: Bachelors degree in Electrical/Computer Engineering with 12 years of hands-on ASIC STA and timing closure experience.
• Technical Expertise: Expert proficiency in sign-off tools (PrimeTime/Tempus) and advanced MMMC/OCV management.
• Automation & AI: Strong scripting skills (Tcl Python Perl Shell) paired with a proven record of utilizing AI plugins and data-mining scripts for runtime reduction and reporting.
• Soft Skills: Exceptional problem-solving and communication abilities.

Compensation and Benefits

As a valued member of our team youll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant but also annual equity awards connecting your success directly to the companys growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical dental and vision plans 401(K) participation including company matching Employee Stock Purchase Program (ESPP) Employee Assistance Program (EAP) company paid holidays paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race color creed religion sex sexual orientation national origin citizenship disability status medical condition pregnancy protected veteran status or any other characteristic protected by federal state or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA please be sure to fill out a home address as this will be used for future correspondence.