Pre-Silicon Digital Verification Engineer

Pre-silicon digital verification engineer for mixed signal integrated an accomplished team at Apple developing custom integrated circuits for Apples existing and future product lines. As a member of our mixed signal ASIC team you will be responsible for verifying complex digital IPs. You will work with the system architects and digital designers making block level specifications clear and precise. You will use the specifications to build verification plans to exercise the functional performance stress cases and error conditions in your blocks. You will own the creation of the verification testbenches using formal verification and UVM based simulation. Then you will build the testcases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for your will participate in code reviews of other blocks in the chips offering proposals to more efficiently achieve our goal of bug free designs on the first addition to traditional digital circuit simulation you will have the opportunity to learn and use other verification techniques such as formal verification digital mixed signal verification and analog mixed signal simulation using state-of-the-art the team is small we supply silicon to most of Apples industry leading hardware development teams. We have a close-knit high performing team ready to ready to mentor engineers entering the mixed signal ASIC development field. Join us in building Apples next generation products. Do you want to be a part of building the surprise and delight in Apples future products

-tCollaborate in developing precise design specifications for digital control blocks n-tUse design specifications to create block and chip level verification plans.n-tArchitect and create block level verification elementsn-tAssist in architecting chip and system level verification environments.n-tUse System Verilog and UVM to develop drivers tests reference models and checkersn-tDebug test failures and work with designers to develop fixesn-tUse functional and code coverage to track progress and gauge tapeout readiness.

BS and a minimum of 3 years of relevant industry experience

Extensive course work in digital design and computer architecturenFoundation in object oriented programming techniquesnLab courses or work experience with System VerilognFamiliar with constrained random verification techniquesnFamiliarity with clock domain crossing design and verification techniquesnSome course work in analog circuit design