PLL Design Engineer

We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal candidate will possess strong analytical abilities a passion for innovation and extensive experience in designing and implementing PLL architectures and this highly visible role you will drive innovation within a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly.

Our team is responsible for all aspects of silicon development for cellular transceivers with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level. nYou will utilize your virtuoso knowledge to design PLL Circuits and component blocks including some of the following: PLL VCO LO generation Dividers Charge Pumps XTAL and other RF/mixed-signal addition to the above responsibilities you will utilize your technical analysis skills to conduct transistor-level feasibility studies for new RF circuit architectures as well as be responsible for simulation and modeling to design and develop analog and mixed signal solutions for next-generation wireless chips.

As an PLL design engineer you will be responsible for providing clocking solutions for cellular transceiver chips. Responsibilities include:nWorking with platform architects system and digital design groups to define the requirements for PLL and its sub-blocks based on the system with the technology team on process selection for the target transistor-level feasibility studies of RF/mixed-signal circuit blocks and various component blocks including PLL VCO LO generation Dividers Charge Pumps XTAL TDCs DTCs and other RF/mixed-signal transistor-level feasibility studies for new RF circuit architectures and working with platform architects and systems groups to define overall PLL modeling of PLL to derive block-level planning and working with layout designers to implement circuit design with best-practice layout bench-level test plans and validating characterizing and debugging designs through high-volume closely with the mask design team to implement layout views of designs.

BS and 10 years of relevant industry experience required.

Experience designing fractional-N PLLs Digital PLLs sigma-delta PLLs and knowledge of loop design to optimize for phase noise/jitter lock time reference spur area power of device physics and demonstrated ability to apply that to optimize noise power area frequency of PLL of bandgaps bias opamps LDOs feedback and compensation be familiar with Cadence Virtuoso SpectreRF and/or C/Matlab/VerilogA with various RF transceiver architectures and their trade-offs is considered a -up and debugging skills and experience in working with production test engineers to build test plans and design for to stay up to date with industry trends and new technologies to drive continuous with digital design digital verification and system-verilog modeling. nFamiliarity with AI/ML optimization and automation flows.