Junior IC Layout Design Engineer
Job Location:
Job Location:
Richardson, TX - USA
Monthly Salary:
Not Disclosed
Monthly Salary:
Posted on:
4 days ago
Posted on:
Vacancies:
1 Vacancy
Vacancies:
Job Summary
For over 20 years IC Enable has successfully provided design IP IC products services and platform solutions to demanding customers ranging from startups to Fortune 50 companies. Our design and product offerings focus on high-reliability mixed-signal and digital markets while our platform solutions support IDMs foundries and IP providers.
Now is an exciting time to join our team as we continue to advance the semiconductor industry through technology development full-custom ASIC/SoC design and electronics development across the Semiconductor Medical and Defense industries. At IC Enable youll have the opportunity to work alongside experienced engineers on challenging projects while building your skills and growing your career.
Position Overview
IC Enable is seeking a motivated and detail-oriented Junior IC Layout Design Engineer to join our growing team in Richardson Texas. This role is ideal for an early-career engineer with at least one year of industry experience who is eager to expand their knowledge of integrated circuit layout design and physical verification while contributing to innovative mixed-signal analog and digital IC development projects.
Job Location and Work Mode:
- Richardson TX (Hybrid; In Office 3 Days A Week)
Qualifications
The ideal candidate will have:
- Minimum 1 year of experience in IC layout design and physical verification
- ITAR Compliance (U.S. Persons meaning U.S. Citizen or U.S. Green Card Holder)
- Experience using Cadence Virtuoso VXL or similar layout design tools
- Familiarity with physical verification tools such as Assura (DRC LVS ERC) or equivalent
- Basic understanding of analog mixed-signal or RF layout concepts
- Knowledge of matching techniques shielding guard rings and latch-up prevention
- Strong analytical troubleshooting and problem-solving skills
- Ability to work effectively in a collaborative team environment
- Strong verbal and written communication skills
- Bachelors degree in Electrical Engineering or a related field
- Exposure to scripting languages such as SKILL or PERL is a plus
- Experience with advanced process technologies FinFET or GAA is a plus but not required
Responsibilities
As a Junior IC Layout Design Engineer you will:
- Support the layout and physical verification of analog mixed-signal RF and custom digital circuits
- Perform layout implementation while adhering to foundry design rules and project requirements
- Assist with DRC LVS ERC and other physical verification activities
- Collaborate with design engineers to optimize layouts for performance area reliability and manufacturability
- Participate in design reviews and contribute to layout quality improvements
- Help identify and resolve layout and verification issues
- Learn and apply best practices for advanced IC layout methodologies
- Contribute to project schedules and deliverables while maintaining high-quality standards
- Support continuous improvement initiatives across design and layout processes
Why IC Enable
At IC Enable we know our most valuable asset is our team. We are looking for individuals who are ready to learn grow and contribute in a collaborative environment. We build our team around people who are humble hungry and smart and we are committed to helping our employees develop their careers through mentorship and hands-on technical experience.
At IC Enable we know that our most valuable asset is our team. We are seeking a candidate who is ready to dive in to our culture and grow with our team. We build our team around those that are humble hungry and smart!
IC Enable benefits include Medical Dental Vision and Ancillary benefits 401K Plan with Company Match program.
IC Enable is an Equal Opportunity Employer
Required Experience:
Junior IC
About Company
Experience You Can Trust. Serving multiple high-tech industries, IC Enable delivers precision quality integrated circuit design projects with first-past success.
