FPGA Design Engineer

Position Description:Position SummaryThe National Radio Astronomy Observatory (NRAO) is a prestigious research and development organization that plays a vital role in the study of the universe. Associated Universities Inc. (AUI) is a nonprofit organization that manages and operates the NRAO under a cooperative agreement with the National Science Foundation. The Observatory is a hub for technological and scientific collaboration operating state-of-the-art radio telescope facilities for use by the international scientific community. The Observatory has been instrumental in the study of black holes galaxies and the early Central Development Laboratory (CDL) at the National Radio Astronomy Observatory (NRAO) is seeking an experienced FPGA Design Engineer to join its digital design team. The engineer will support the design and implementation of a new digital signal processing system for a next-generation radio telescope synthesis digital design team develops cutting-edge systems that enable advances in radio astronomy supporting research into galaxy formation star and planet origins and black selected candidate will contribute to the design implementation and verification of embedded processor-based FPGA systems with an emphasis on disciplined timing-driven design and robust verification within a small centralized team the engineer will collaborate across internal groups and contribute to systems shared with the international scientific community. The role requires strong time management the ability to handle multiple concurrent efforts and effective cross-disciplinary location for this position will be based at the Central Development Laboratory in Charlottesville You Will be Doing:Design and implement embedded FPGA-based systems with a focus on performance reliability and timing closure Apply disciplined RTL design practices and sound synchronous design techniques including management of clock domain crossings Develop and execute verification strategies including self-checking testbenches and end-to-end system validation Perform static timing analysis develop constraints and drive designs to timing closure Translate algorithmic and DSP models into efficient FPGA implementations Contribute to reusable IP and scalable design architectures Work across multiple concurrent efforts collaborating within a small centralized team and with external partners Document designs verification approaches and technical decisions clearlyWork EnvironmentWork is mission driven team oriented and typically performed in an office setting within a research or development environment. Who You Are:EducationBachelors degree in electrical engineeringExperienceFive years of FPGA development experience in complex digital systems Strong proficiency in RTL design and hardware description languages Solid understanding of digital design fundamentals and FPGA implementation flows (synthesis through place-and-route) Experience with modern verification methodologies and design-for-verification practices Experience with embedded processor-based FPGA systems like (Intel Agile-X or similar) and high-speed or high-bandwidth interfacesFamiliarity with DSP concepts and version control Strong problem-solving ability and effective written and verbal communication skillsSkills and CompetenciesHigh level of competency in Microsoft software products and web-based systems Visio and to detail is criticalHighly organizedExcellent communication skillsAdditional RequirementObservatory employees must be authorized to work in the United States. The Observatory presently cannot sponsor H-1B Visas for this Rewards:CompensationThe starting salary of this position is between $90015-$126000. Factors which may affect starting pay within this range may include; education experience skills competencies other qualifications of the successful candidate as well as internal equity and labor market :Associated Universities Inc (AUI) offers a comprehensive benefits package addressing the needs of employees and their families with most benefits beginning on the first day of employment subject to eligibility requirements. AUI provides:Excellent paid time off (13 holidays annual accrual of up to 24 vacation days)Medical dental and vision plans are effective on the first day of retirement benefit contributes an amount equal to 10 percent of a qualified participants base pay with no required employee Total Rewards for more Instructions:Select the Apply button above. Please be prepared to upload your current CV/Resume and a cover letter describing interest and suitability for the Opportunity Employer Statement:AUI is an equal opportunity employer. To view our complete statement please visit If you require reasonable accommodation for any part of the application or hiring process you may submit your request by sending an email to PM20