Design Automation Standard Cell Characterization Engineer
San Jose, CA - USA
Job Summary
We are seeking a Design Automation / Library Characterization Engineer to lead development and delivery of standard cell library flows automation and quality infrastructure for advanced NAND/ASIC programs. This role will also support Digital Frontend (DFE) enablement bridging library development with synthesis and timing signoff requirements.
Key Responsibilities
- Standard cell library characterization and release flows
- Work on end-to-end characterization (nominal low voltage) using tools like Liberate/Siliconsmart
- Deliver complete library collaterals (.lib LEF GDS CDL Verilog NDM etc.)
- Develop and enhance DA automation frameworks
- Build scalable automation using Python Perl Tcl and shell scripting
- Improve flow efficiency (runtime reduction reuse models incremental characterization)
- Drive library QA and validation infrastructure
- Develop QA flows for cross-collateral consistency (lib netlists layouts timing views)
- Implement equivalency checks validation dashboards and automated reporting
- Support Digital Frontend (DFE) enablement
- Partner with frontend teams to ensure high-quality library deliverables for synthesis and STA
- Enable flows for Design Compiler / Fusion Compiler and PrimeTime integration
- Validate timing models constraints and library views for RTL-to-Gates and timing closure flows
- Support debugging of synthesis and timing issues related to library quality and modeling
- Enable multi-release and cross-version comparisons
- Build tools for library comparison (timing power leakage constraints)
- Support regression validation across process and voltage corners
- Support PnR and full-chip integration flows
- Contribute to APR collateral generation (NDM FRAM AOCV IR etc.)
- Execute flows from netlist to GDS (floorplan timing closure verification)
- Improve ECO and design closure productivity
- Enhance ECO automation flows (e.g. Conformal/ICC2 flows)
- Reduce manual debug time via automation (antenna fixes constraint handling)
- Partner cross-functionally
- Work with RTL frontend backend PDK and CAD teams to align flows and deliverables
- Support fast-paced tapeouts with high-quality production-ready libraries
Qualifications :
- MS in Electrical Engineering or a related field
- 5 years of experience in standard cell library characterization and validation including generation and delivery of production-quality collaterals
- 5 years of experience in design automation and EDA flow development with a focus on scalable and maintainable methodologies
- Hands-on experience with digital frontend flows including synthesis and static timing analysis (STA)
- Strong expertise with Synopsys tools including Siliconsmart Fusion Compiler Design Compiler and PrimeTime
- Experience with Cadence tools including Virtuoso and Conformal
- Strong scripting proficiency in Python Perl Tcl and Bash applied to flow development automation and debug
Preferred Qualifications
- Deep experience in library enablement for RTL-to-GDSII flows including integration across synthesis STA and physical design
- Strong expertise in timing model validation and constraint development ensuring accuracy across design scenarios
- Hands-on experience with AOCV and variation-aware timing methodologies
- Proven experience building QA/validation frameworks and large-scale automation systems to improve flow robustness and efficiency
- Experience developing or supporting frontend debug flows including synthesis QoR analysis and timing closure debug
- Familiarity with MCMM design methodology including setup and debug across multi-mode/multi-corner scenarios
- Exposure to NAND/ASIC tapeout environments and end-to-end design flows
Additional Information :
This position is also eligible to participate in Solidigms restricted stock unit (RSU) restricted cash unit (RCU) and cash bonus addition Solidigm offers a benefits package that includes medical dental vision supplemental life and AD&D insurance; short- and long-term disability; healthcare and dependent care flexible spending accounts and a company match on eligible 401(k) plan contributions.
The compensation range for this role is $121280 - $194100. Actual compensation is influenced by a variety of factors including but not limited to skills experience qualifications and geographic location.
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Remote Work :
No
Employment Type :
Full-time
About Company
Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with ... View more