ASIC Physical Design

Here is an ASIC Physical Design role

MUST be onsite in the Bay Area though if you can find candidates that are already there.

Spots: Position 1:

Location: Onsite San Jose CA

Duration: 6-9 Months (will extend)

Interview Process: 1 phone 1 panel onsite 1 zoom

Skills/JD:

Physical Design engineer to own the entire block
Floorplanning PlacenRoute Timing Closure
DRC/LVS checks
Low nm experience preferred
Cadence tooling - They are using Innovus and Voltus mostly
Synopsys tools for Timing Analysis

I have summarized the job requirements below:

• Good understanding of Cadence tools (Innovous Quantus Voltus).
• Deep knowledge about industry standards in Physical Design Physical aware synthesis Floorplanning CTS and place and route.
• Experience in developing and implementing Power-grid and high speed clock constraints and specifications.
• Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.
• Experience with CDC static timing analysis methodologies and relevant tools.
• Understanding and experience ofmixedsignal environments is a must.

Regards

Manju Sharma (Business Unit Head)
Vaarida Technologies