ASIC Design Engineer — Neural Engine DMA

Computational photography live language translation and countless other on-device AIncapabilities depend on moving enormous amounts of data between memory and compute atnexactly the right time. As part of our Silicon Engineering Group you will helpnbuild the high-performance DMA engines responsible for moving model weights and activationntensors between the memory subsystem and the Apple Neural this role you will collaborate closely with architecture and verification teamsnacross the full front-end design cycle. The work you contributenships in Apple products used by billions of people every day.

As an ASIC Design Engineer on the ANE DMA Design team you will contribute to the designnof DMA subsystem blocks from microarchitecture specification through -performance DMA involves hard problems in data movement throughput and this front-end design role your work will include:nn- Writing well-parameterized RTL structured for correct synthesis clean timing and lown power along with assertions and cover points that encode design intent and ensuren verification completeness.n- Executing front-end implementation tasks: synthesis timing closure area and powern analysis linting and logic equivalence checks.n- Collaborating with fellow designers and architecture teams to understand designn requirements contribute to micro-architectural specifications and develop solutionsn that meet performance power and area targets.n- Working closely with design verification and formal verification teams to ensuren functional correctness: reviewing test plans debugging failures and ensuring then designs intended behavior is fully exercised.

Bachelors Degree plus 0 years of industry experience

Familiarity with Verilog or SystemVerilog and core digital design fundamentals: finiten state machines pipelining parallelism and exposure to on-chip bus protocols such as AMBA (AXI AHB APB).nInterest in or exposure to system-level concepts: how data moves through a SoC flown control between producers and consumers memory system latency and bandwidth trade-offsn and how hardware and software divide responsibilities at system in or curiosity about high-bandwidth domains: networking image and videon processing multimedia or AI/ with scripting languages (Python Perl Tcl) for design technical writing skills and the habits of asking good questions flagging issuesn early and contributing constructively in design reviews.