Principal Test EngineerDFT Architect

Test and DFT Architecture

Define product-level test and DFT strategy including wafer probe final test characterization qualification GRR production test flow and cost-of-test targets.

Partner with design systems validation product engineering test engineering quality operations and manufacturing teams to define DFT requirements early in the lifecycle.

Drive requirements for test muxes scan/debug access analog observability digital controllability embedded monitors BIST where applicable trim/calibration access fuse/NVM test modes and diagnostic hooks.

Review schematics architecture documents specifications register maps and test-mode plans to identify testability gaps before design freeze.

Establish reusable DFT and test-access standards for power analog mixed-signal and digitally assisted products.

ATE and Production Test Strategy

Define ATE platform strategy including tester selection instrument usage multisite targets handler/prober compatibility hardware reuse test-time optimization and production scalability.

Establish strategic test flows binning methodology screen strategy guardband approach data collection strategy and test naming conventions.

Assess feasibility for critical tests such as high-voltage stress analog parametric measurements digital interface testing trim/calibration NVM programming wafer-level characterization and production diagnostics.

Influence test hardware architecture including load boards probe cards sockets change kits and interface circuitry to improve accuracy signal integrity and multisite scalability.

Guide platform-transition strategies and production test readiness for new products and product families.

Circuit and Testability Leadership

Apply circuit-level knowledge to ensure key internal nodes bias conditions clocks references protection circuits calibration loops and failure mechanisms are observable and controllable on ATE.

Work with design teams to ensure critical analog digital and power-management functions can be accurately measured in production.

Evaluate the impact of circuit architecture wafer-test strategy package choice and test platform capability on test coverage yield learning quality risk cost and cycle time.

Support complex silicon and production debug by connecting ATE data bench data circuit behavior design intent process variation and production yield trends.

Identify testability risks early including limited test access insufficient characterization coverage weak diagnostics limited traceability or late test-mode definition.

Cross-Functional Influence

Serve as senior technical interface between design DFT test engineering product engineering validation quality operations and manufacturing partners.

Lead testability reviews at key development gates and ensure issues are resolved before tape-out qualification or production release.

Create test architecture documentation DFT checklists coverage expectations production-readiness criteria and product-family test strategy templates.

Mentor engineers on DFT principles ATE methodology debug strategy and scalable production test development.

Influence roadmap decisions for ATE platforms test data infrastructure characterization automation production analytics and AI-enabled test optimization.

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Qualifications :

Bachelors degree in Electrical Engineering Computer Engineering or related field; advanced degree preferred.

Typically 12 years of semiconductor experience in test engineering DFT product engineering validation design or product industrialization.

Strong hands-on experience with ATE test development and production test strategy.

Experience with analog mixed-signal digital and/or power-management IC test.

Strong understanding of ATE instrumentation timing digital pattern execution analog measurements multisite test handler/prober interfaces test hardware and production data.

Working knowledge of circuit design concepts including references regulators ADC/DACs digital interfaces clocks trims NVM/fuse structures protection features and test-access circuitry.

Familiarity with wafer sort/final test strategy production test flows yield learning quality screening and test-cost modeling.

Ability to read schematics block diagrams design specs register maps test plans and characterization/yield data.

Strong debug capability using ATE results bench measurements simulation data failure-analysis inputs and production trends.

Experience with scripting automation and data analysis tools such as Python JMP MATLAB SQL or equivalent.

Demonstrated ability to lead cross-functional technical reviews and influence without direct authority.

Preferred Qualifications

Experience with power-management automotive high-voltage mixed-signal or digitally assisted analog products.

Experience with ATE platforms such as Advantest V93K Teradyne/Microflex ETS COHU/DiamondX SPEA or similar.

Familiarity with scan BIST memory test boundary scan test access protocols and digital DFT methods.

Experience with trim/calibration architecture fuse/NVM programming wafer sort final test production diagnostics and test-time reduction.

Knowledge of NPI gates production release characterization qualification GRR and test readiness.

Experience with yield analysis guardbanding statistical methods test-cost modeling quality screening and production data analysis.

Familiarity with AI/ML or advanced analytics applied to semiconductor test and production data is a plus.

Key Skills

Semiconductor ATE and production test expertise

DFT and testability architecture

Circuit-aware problem solving

Cross-functional technical leadership

Test cost quality yield and coverage optimization

Structured silicon and production debug

Strong data analysis communication and mentoring skills

Ability to define reusable methodology across product families

Success Measures

Testability requirements are defined before tape-out.

Product test flows meet quality coverage cost cycle-time and production-readiness targets.

Critical analog digital trim NVM and diagnostic functions are measurable on ATE.

Testability reviews reduce late design changes production surprises and post-silicon debug cycles.

ATE platform hardware package/test and multisite strategies support scalable production.

Test architecture improves reuse yield learning and production readiness across product families.

Additional Information :

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. As the industrys leading expert in embedded processing with unmatched quality and system-level know-how we have evolved to provide scalable and comprehensive semiconductor solutions for automotive industrial infrastructure and IoT industries based on the broadest product portfolio including High Performance Computing Embedded Processing Analog & Connectivity and Power.
 
With a diverse team of over 22000 professionals in more than 30 countries we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable power-efficient solutions today that help people and communities thrive tomorrow To Make Our Lives Easier.     
 
At Renesas you can: 

• Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.  

• Make a real impact by developing innovative products and solutions to meet our global customers evolving needs and help make peoples lives easier safe and secure. 

• Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system including the remote work option and Employee Resource Groups will help you excel from the first day.    

Are you ready to own your success and make your mark  

Join Renesas. Shape Your Future with Us.  

Renesas Electronics is an equal opportunity and affirmative action employer committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by federal state or local law. For more information please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.

Remote Work :

No

Employment Type :

Full-time