Digital Hardware Designer
Share
Job Location:
Dallas, IA - USA
Monthly Salary:
Not Disclosed
Posted on:
Yesterday
Vacancies:
1 Vacancy
Job Summary
Job Description: Digital Hardware Designer
Role Overview
We are looking for a Digital Hardware Designer to contribute to the design and
development of next-generation adaptive compute platforms and communication
systems.
The role involves RTL design micro-architecture development and integration of high-
performance digital blocks for SoCs FPGAs and ASICs targeting AI networking and
embedded applications.
Key Responsibilities
1. RTL Design & Micro-Architecture
Design and implement high-quality RTL (Verilog/SystemVerilog/VHDL)
Develop micro-architecture specifications from system-level requirements
Work on complex digital blocks such as:
o High-speed interfaces (PCIe Ethernet DDR)
o Compute engines (AI/ML accelerators DSP blocks)
o Control and data-path logic
1. RTL Design & Micro-Architecture
Design and implement high-quality RTL (Verilog/SystemVerilog/VHDL)
Develop micro-architecture specifications from system-level requirements
Work on complex digital blocks such as:
o High-speed interfaces (PCIe Ethernet DDR)
o Compute engines (AI/ML accelerators DSP blocks)
o Control and data-path logic
2. SoC / FPGA Integration
Integrate IPs into SoC / FPGA subsystems
Work on interconnects (AXI NoC) and system-level design
Support multi-die / chiplet-based architectures
Collaborate on clocking reset and power domains
Integrate IPs into SoC / FPGA subsystems
Work on interconnects (AXI NoC) and system-level design
Support multi-die / chiplet-based architectures
Collaborate on clocking reset and power domains
3. Verification & Validation Support
Work closely with verification teams for:
o Testbench development
o Debugging functional issues
Perform:
o RTL simulation and debugging
o Lint CDC (Clock Domain Crossing) and RDC checks
Support post-silicon bring-up and debugging
Work closely with verification teams for:
o Testbench development
o Debugging functional issues
Perform:
o RTL simulation and debugging
o Lint CDC (Clock Domain Crossing) and RDC checks
Support post-silicon bring-up and debugging
4. Performance & Power Optimization
Optimize designs for:
o Performance (latency/throughput)
o Area and power efficiency
Implement low-power techniques:
o Clock gating
o Power gating (with UPF/CPF alignment)
Optimize designs for:
o Performance (latency/throughput)
o Area and power efficiency
Implement low-power techniques:
o Clock gating
o Power gating (with UPF/CPF alignment)
5. Cross-Functional Collaboration
Collaborate with:
o Architecture teams for feature definition
o Physical design teams for timing closure
o Firmware and validation teams for system bring-up
Contribute to design reviews and documentation
Collaborate with:
o Architecture teams for feature definition
o Physical design teams for timing closure
o Firmware and validation teams for system bring-up
Contribute to design reviews and documentation
Required Skills & Qualifications
Education
/ in Electronics / Electrical / VLSI / Computer Engineering
Education
/ in Electronics / Electrical / VLSI / Computer Engineering
Experience
3 10 years in Digital Design / RTL Development
Technical Skills
Strong expertise in:
o Verilog / SystemVerilog / VHDL
o Digital design fundamentals (FSMs pipelining timing analysis)
Good understanding of:
o SoC architecture and integration
o High-speed interfaces (PCIe DDR Ethernet USB)
o Clocking resets and CDC concepts
Experience with tools:
o Simulation (VCS ModelSim Xcelium)
Strong expertise in:
o Verilog / SystemVerilog / VHDL
o Digital design fundamentals (FSMs pipelining timing analysis)
Good understanding of:
o SoC architecture and integration
o High-speed interfaces (PCIe DDR Ethernet USB)
o Clocking resets and CDC concepts
Experience with tools:
o Simulation (VCS ModelSim Xcelium)
o Lint/CDC tools (SpyGlass Questa CDC)
Familiarity with:
o Scripting (Python Perl Tcl)
Familiarity with:
o Scripting (Python Perl Tcl)
Preferred Skills
Experience in Adaptive Compute / FPGA platforms (e.g. Xilinx/AMD)
Exposure to:
o AI/ML accelerators or networking SoCs
o Automotive (ADAS EV platforms)
Knowledge of:
o Low-power design methodologies (UPF/CPF)
o Hardware-software co-design
Experience in Adaptive Compute / FPGA platforms (e.g. Xilinx/AMD)
Exposure to:
o AI/ML accelerators or networking SoCs
o Automotive (ADAS EV platforms)
Knowledge of:
o Low-power design methodologies (UPF/CPF)
o Hardware-software co-design
Behavioral Competencies
Strong analytical and debugging skills
Ability to work in fast-paced cross-functional environments
Effective communication and documentation skills
Ownership and accountability for deliverables
Strong analytical and debugging skills
Ability to work in fast-paced cross-functional environments
Effective communication and documentation skills
Ownership and accountability for deliverables
Typical Applications in ACC Domain
AI/ML compute engines
Smart NICs and networking processors
Embedded and edge compute platforms
Automotive compute systems (ADAS infotainment)
AI/ML compute engines
Smart NICs and networking processors
Embedded and edge compute platforms
Automotive compute systems (ADAS infotainment)
