Lead ASIC DFT Engineer
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Job Location:
San Jose, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
2 hours ago
Vacancies:
1 Vacancy
Job Summary
Role: Lead ASIC DFT Engineer
Location: San Jose CA
Work Setup: Remote however once/month in office. PST time zone preferred
Designation: Associate
Location: San Jose CA
Work Setup: Remote however once/month in office. PST time zone preferred
Designation: Associate
Experience Required:
- 10 years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect implement verify and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture scan insertion ATPG MBIST/LBIST JTAG boundary scan and post-silicon validation along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
We are seeking a highly experienced Lead ASIC DFT Engineer to architect implement verify and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture scan insertion ATPG MBIST/LBIST JTAG boundary scan and post-silicon validation along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
Key Skills Required:
- Strong hands-on ASIC DFT experience with end-to-end ownership
- Deep expertise in scan architecture ATPG MBIST LBIST JTAG boundary scan and silicon debug
- Experience with Synopsys Cadence and Siemens/Mentor EDA tools
- Strong background in scan insertion scan chain stitching ATPG setup simulation debug and DRC analysis
- MBIST implementation and verification; SMS experience preferred
- Tessent/SSN experience preferred
- Strong understanding of PLLs RTL design synthesis LEC and physical design flows
- Post-silicon debug and silicon bring-up experience
- TCL PERL or Python scripting experience is highly preferred
