Director of DV for MEMPCIE COE

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

- Define and scales UVMbased verification environments drive reuse across IP and programs and ensures comprehensive functional and code coverage.

- Collaborates with architecture design firmware SOC and post-silicon teams to influence specifications early and reduce downstream verification risk.

- Manages globally distributed DV teams develops technical depth and future leaders.

- Accountable for DV schedules risk assessment coverage closure and transparent communication of tapeout readiness to senior management and key stakeholders

- Review and resolve cross-program technical issues and escalations

- Engage with ecosystem partners (JEDEC IP vendors PHY providers) on interoperability and enablement

What Were Looking For

The Custom Cloud Solutions Group (CCS) is looking for a DV Technical Director with a demonstrated track record of success in launching products with specific expertise in PCIe and Memory technologies. The person will be responsible for high-quality predictable delivery of scalable PCIE and Memory subsystems as part of the center of excellence (COE) to all CCS SOC products in 2027 and beyond. A Director of Design Verification for PCIe and Memory must combine deep protocol expertise systemlevel thinking scalable UVM methodology leadership and strong people management to ensure A0 silicon production for complex SoCs. Requirements include:

- BS/MS/PhD in Computer Science Electrical Engineering or Computer Engineering with 10-15 years of relevant professional experience.
- Background in creating test plans and designing test bench architectures that are hierarchical reusable and scalable.
- Background in SOC verification and test bench development using UVM and System Verilog object-oriented programming and constrained random
methods.
- Experience with EDA verification and debugging tools scripting languages such as Python or Perl and revision control systems.
- Effective communication and teamwork skills
- Mindset for high quality and attention to detail
- Independent learner proactive in problem-solving and finding creative solutions

- a good understanding of PCIE architectures and memory technologies (DDR LPDDR HBM).

- proven track record of owning complex subsystems end-to-end across multiple products.

- proven track record of leading distributed diverse teams across sites.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.