Lead Software Engineer ( Verification )
Job Summary
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Verification ( SV UVM & VHDL )
Cadence is a pivotal leader in electronic design building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer hyperscale computing 5G communications automotive aerospace industrial and health.
The Cadence Advantage
- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative innovative and to make an impact.
- Cadences employee-friendly policies focus on the physical and mental well-being of employees career development providing opportunities for learning and celebrating success in recognition of specific needs of the employees.
- The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success.
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
- You get to work with a diverse team of passionate dedicated and talented individuals who go above and beyond for our customers our communities and each otherevery day.
Job Summary:
We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This position requires the technical expertise in protocol and formal verification methodologies.
This an excellent opportunity to work in a supportive and friendly work environment where we are vested in each others success and are passionate about technology and innovation.
Work location: Bangalore
Experience : 5 - 8 Years or equivalent relevant experience
Education : M.E./MTech (Electronics or similar) or B.E/BTech. (Electronics or similar)
JD
Position Description:
Were looking for talented SW engineer to join us and be part of a team that is responsible for developing Cadence SW driven verification Solutions.
Duties will include active development and support of verification libraries for different architectures-based systems and other IPs.
The candidate must have background in verification and verification methodologies very strong problem-solving skills and written and verbal communication skills.
SW Engineers are expected to
Develop verification products based on the multiple customer requirements
Analyze customer requirements and translate them to product enhancements bringing their technical understanding of the customer needs and issues
Provide active support and guidance to customer issues
Collaborate with other team members and different functions in the organization such as PV and field
Position Requirements:
- in Electronics and communication
- Strong programming skills (OOP)
- Background in developing IP Sub-system SoC level verification environment with both UVM and SW-driven (embedded c)
- Excellent verbal and written communications skills
- Strong interest and understanding of design and verification methodologies
- Strong problem solving and analytical skills
- UNIX shell scripting
Strong Plus:
Experience with System Verilog Specman e VHDL Verilog
Working knowledge of embedded c
Knowledge of protocols such as AMBA PCI-E USB Ethernet 10 Gig NVMe etc.
Understanding of verification methodologies (UVM)
Prior experience in metric driven functional verification
Regards
Madhu
Were doing work that matters. Help us solve what others cant.
Required Experience:
IC
About Company
Do you want to shape the future of technology? Cadence is leading the charge to solve some of technology’s toughest challenges. We work with the world’s most innovative companies, across a growing range of industries. Major trends that you hear about everyday – like artificial intell ... View more