Senior Engineer I – Verification

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Job Description:

Job Summary

We are seeking a highly skilledSenior Engineer I Verificationwith a strong understanding offull-chip verificationandexposure to AMS (Analog/Mixed-Signal) environments. This role focuses on ensuring functional correctness and quality of complex SoC designs by developing and executing robust verification strategies across digital and mixed-signal domains.

Key Responsibilities

• Lead and contribute tofull-chip verificationfor complex SoC and mixed-signal designs
• Develop and executeverification plans testbenches and methodologiesusing SystemVerilog and UVM
• Collaborate withAMS digital design and architecture teamsto validate mixed-signal behavior
• Integrate and verifyanalog IP interactionswithin full-chip and subsystem environments
• Drivecoverage closure(functional code and assertions) at block subsystem and full-chip levels
• Debug and resolve complex failures involvingdigital analog and interface interactions
• Support power-aware reset and clock-domain verification
• Mentor junior engineers and promote verification best practices
• AI- Skills
  • Leverage AI/ML tools to improveRTL development verification productivity and debug efficiency.
  • Use and prompt LLM based assistants to generate code stimuli documentation root cause analysis and scripting
  • Apply AI driven techniques for log analysis waveform triage and failure clustering
  • Ability to design run and analyzeAIassisted trials/experimentsto improve productivity or quality
  • Know-how of integrating AI tools withexisting EDA flows and scripts.

Requirements/Qualifications:

• Bachelors or Masters degree inElectronics Engineering or related field
• 5 years of experience inASIC/SoC verification
• Strong expertise inSystemVerilog and C based coding for verification
• Solid understanding offull-chip SoC architecture and integration
• Exposure to AMS verification concepts including interaction between analog and digital domains
• Experience with simulation debugging and coverage analysis tools
• Proficiency in scripting languages such asPython Perl or Shell
• Strong analytical debugging and communication skills

Preferred Qualifications

• Hands-on experience withAMS simulators or mixed-signal verification flows
• Familiarity withreal-number modeling (RNM)or behavioral modeling of analog blocks
• Experience withlow-power verificationand power-aware simulations
• Knowledge offormal verificationmethodologies
• Experience verifying interfaces such as PLLs ADCs/DACs or power management blocks
• Prior mentoring or technical leadership experience

Travel Time:

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