FPGA Design Engineer

Who Youll Work With

As a core member of the FPGA Design and Verification team the candidate will be part of a fast-paced high caliber team Designing and Verifying control path FPGAs for Arista Network products used in the computer networking industrys largest data centers. The FPGA Design Engineer is responsible for all aspects of the control path FPGA from collecting the functional requirements that are needed to reviewing the schematics of the board design engineer to verifying the design using the latest tools to bring-up and support of such a vital part of the networking hardware design.  The successful candidate will work closely on a project from its early conception to the customer shipment and support when needed. They will work with fellow engineers and members of the hardware software and manufacturing team to understand the feature requirements design and validate it. Besides closely working with the hardware engineers in designing the board they will also review the hardware specifications and take ownership of the control path FPGA. 

What Youll Do 

• Verilog/System Verilog code development integration simulation and testbench creation  
• Perform FPGA implementation including synthesis place and route timing analysis and debug 
• Collaborate with hardware and software engineers for rapid system-level bringup and debugging of network switch designs
• Participate in fpga level code reviews as well as schematic and board design reviews
• Incorporate scripting to process input/output data for FPGA toolchains

Concepts and Skills You May Learn

• Data and control architectures of a modern ethernet switch including chip IO interfaces such as Interlaken Ethernet PHY/MAC PCIe SMBus SPI MDIO JTAG etc.
• Protocols using Ethernet such as PTP SFlow POE etc.
• Real world applications and the challenges of FPGA design including resource/timing constraints race conditions state machines etc.
• Exposure to multiple FPGA vendor architectures IDEs and toolchains (Xilinx Altera Microsemi etc.)
• Simulation software for FPGA functional verification
• How to read and interpret PCB schematics as they pertain to FPGA code development
• Cross-functional collaboration to ideate and solve system-level technical challenges 

Qualifications :

• 1-5 years of designing Verilog/System-Verilog RTL code
• Control path design experience (Ethernet Data path design experience preferred)
• On-chip bus interfacing design experience e.g. AXI (Streaming bus interfacing design experience preferred)
• FPGA design resource and timing closure experience preferred
• Python/TCL/Scripting experience

Compensation Information 

The new hire base pay for this role has a pay range of $110000 to $170000. 

Arista offers different pay ranges based on work location so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors including skills qualifications relevant experience and work location. 

The pay range provided reflects base pay only and in addition certain roles may also be eligible for discretionary Arista bonuses and equity. Employees in Sales roles are eligible to participate in Aristas Sales Incentive Plan which pays commissions calculated as a percentage of eligible -based employees are also entitled to benefits including medical dental vision wellbeing tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location.  

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Additional Information :

Arista Networks is an equal opportunity employer.  Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race color religion sex sexual orientation gender identity national origin or any other factor determined to be unlawful under applicable federal state or law law.  All your information will be kept confidential according to EEO guidelines.

Remote Work :

No

Employment Type :

Full-time