Analog Layout Mid Level Engineer

You will independently convert schematics into well structured device cell and block level analog/mixed signal layouts using Cadence Virtuoso working closely with senior layout and analog design engineers. You will apply established layout techniques to meet electrical area and reliability requirements and progressively take on more complex production IPs as you deepen your expertise.

• Implement device cell and block layouts for analog/mixed signal circuits (bias/reference blocks amplifiers simple converter sub blocks IO support cells) following internal guidelines.

• Perform basic block floorplanning under supervision ensuring sensible device placement symmetry and routing feasibility.

• Route signals power and ground within assigned blocks with attention to matching shielding and parasitic awareness as directed by Senior/Lead engineers.

• Run DRC/LVS (and related checks) on owned layouts debug common violations and iterate based on review feedback until sign off.

• Generate and maintain extracted views for assigned blocks and support designers in setting up post layout simulations when required.

• Apply standard DFM ESD latch up and reliability practices as documented in team checklists and process guidelines.

• Prepare layouts for higher level integration (clean hierarchy proper pins labels and constraints) to ease pad ring and chip top work done by seniors.

• Participate in design and layout reviews provide task estimates and status for your own deliverables and incorporate review comments systematically.

• 4 6 years of experience in analog/mixed signal IC layout at device cell and block level preferably in SoC or mixed signal ASIC environments.

• Hands on proficiency with Cadence Virtuoso for schematic driven layout placement routing and basic floorplanning.

• Working knowledge of DRC/LVS flows using tools such as Mentor Calibre or equivalent including routine debugging of rule and connectivity issues.

• Solid grasp of CMOS layout fundamentals: wells guard rings dummy devices basic matching concepts shielding and awareness of noise and coupling.

• Familiarity with analog layout constraints (matching parasitics current density IR drop) and strong motivation to deepen expertise in high speed RF and power management layouts by learning from Senior/Lead engineers.

• Ability to follow documented flows naming conventions and checklists accept feedback positively and collaborate effectively with more senior team members.

• B.E./ or M.E./ in Electronics Electrical VLSI or related discipline.

• 4 6 years of relevant experience as an Analog/AMS/IC Layout Engineer working in CMOS technologies.