Senior FPGA Engineer

Position Title:Senior FPGA Engineer
Requisition ID:1699
Position Location:Fairfax VA
Position Reports To:Senior Manager FPGA Engineering
Supervises Others:No

At Trident Systems Space Electronic Systems (SES) division we believe in the power of using strong engineering principles to drive innovation and solve complex problems. We foster a culture of rigorous engineering and continuous improvement leveraging the full knowledge of our organization through collaborative product development processes that include design and peer reviews. We combine our expertise in space electronics with right-sized development processes to create innovative high-performance space-based electronic systems that meet our customers evolving needs.

We are a mission partner supporting DoD Intelligence Community and Civil space customers. We develop complex radiation effects mitigated designs that balance competing requirements in modern space programs delivering cutting-edge solutions that enable our customers to achieve more in space.

Position Summary

The Senior FPGA Engineer will play a critical role in the design and development of advanced FPGA solutions supporting cutting-edge space-based electronic systems. This position is responsible for architecting implementing and verifying complex high-speed programmable logic designs for Software Defined Radios (SDRs) On-Board Processors (OBPs) and storage solutions using the latest AMD (Xilinx) technologies. The ideal candidate brings deep expertise in RTL design timing closure simulation and system integration and thrives in a collaborative multi-disciplinary environment delivering mission-critical solutions to DoD Intelligence Community and Civil space customers.

Duties and Responsibilities

• Work within a multi-discipline team of engineers designing Software Defined Radios (SDRs) On-Board Processors (OBPs) and storage solutions for space applications utilizing the latest Xilinx (AMD) technologies (e.g. Zynq Ultrascale MPSoC Zynq Ultrascale RFSoC and Versal ACAP)
• Create and maintain complete FPGA designs using a combination of VHDL and Vivado IP Integrator with a strong emphasis on efficient data path architecture reliable timing closures and high-performance implementations
• Code simulate and verify a wide range of RTL modules for FPGAs including modules for digital signal processing (DSP) control algorithms interfaces to external peripherals etc.
• Design and implement solutions that use embedded ARM processors DDR4 memory high-speed serial interfaces such as Aurora JESD204B/C PCIe 1G/10G/100G Ethernet etc.
• Create and maintain comprehensive simulation test bench modules to ensure a high degree of code coverage and verify functionality of firmware modules
• Create and maintain Timing Constraints to ensure design is fully constrained and consistent Timing Results are achieved post-implementation
• Create and maintain IP core level and Top-Level design documents
• Participate in code reviews design reviews and contribute towards FPGA Design methodologies and best practices
• Work in close collaboration with hardware and software engineers throughout the integration process to ensure that FPGA designs are correctly implemented
• Mentor junior engineers: provide training guidance and support as needed
• Ability to support travel or off-site work as needed
• Perform other duties as assigned

Required Qualifications

• Bachelors degree in Computer Engineering Electrical Engineering or related technical degree
• 6 years of related experience with a bachelors degree OR a 4 years of experience with a masters degree
• Experience with firmware design simulation and verification
• Thorough understanding of FPGA design methodology including physical synthesis static timing analysis place/route verification power analysis and timing closure techniques
• Experience designing with Xilinx SoC/FPGA devices using the Vivado Design Suite
• Experience using Vivado IP Integrator
• Experience with RTL logic design and coding using VHDL
• Experience writing simulation testbenches to identify bugs and verify designs using SystemVerilog
• Experience with board bring-up/verification in an electronic lab environment and use of FPGA ILA-based debugging tools such as Vivado HW Debugger Chipscope SmartDebug

Preferred Qualifications

• Experience programming and implementing designs using the Versal AI Engines
• Experience designing with Microsemi (Microchip) FPGAs using Libero
• Experience using revision control systems such as Git
• Experience using Modelsim/Questasim and/or Aldec simulation tools
• Experience using simulation verification libraries such as UVVM UVM OVM etc.
• Familiarity with lab test equipment such as logic analyzers oscilloscopes signal generators spectrum analyzers etc.
• Highly productive self-motivated person able to contribute as an individual and work within a distributed team
• Digital Signal Processing (DSP)
• MATLAB and Simulink
• Linux
• C/C
  
  

Benefits

Hired applicants may be eligible for benefits including but not limited to:

• Health benefits
• Medical
• Dental
• Vision
• Basic life with AD&D
• Short term disability
• Long term disability
• Ancillary (Voluntary life with AD&D accident critical illness hospital and pet)
• Spending accounts (HSA FSA and DCFSA)
• Paid time off
• Holidays
• 401(k) (including company match)
• Tuition reimbursement
• Leaves (Parental maternity and military)
• Annual discretionary bonus (for eligible roles)

Trident Systems reserves the right to change or assign other duties to this position.

Trident Systems is an affirmative action and equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race color religion age sex national origin disability status genetics protected veteran status sexual orientation gender identity or expression or any other characteristic protected by federal state or local laws. To request reasonable accommodation to participate in the job application or interview process please contact.

Pay Transparency: The contractor will not discharge or in any other manner discriminate against employees or applicants because they have inquired about discussed or disclosed their own pay or the pay of another employee or applicant. However employees who have access to the compensation information of other employees or applicants as a part of their essential job functions cannot disclose the pay of other employees or applicants to individuals who do not otherwise have access to compensation information unless the disclosure is (a) in response to a formal complaint or charge (b) in furtherance of an investigation proceeding hearing or action including an investigation conducted by the employer or (c) consistent with the contractors legal duty to furnish information. 41 CFR 60-1.35(c)