Principle Physical Verification Engineer

San Jose, CA - USA

Monthly Salary: Not Disclosed

Posted on: Yesterday

Vacancies: 1 Vacancy

Job Summary

Principle Physical Verification Engineer

Fulltime

San Jose CA

Role Overview

We are looking for a hands-on Physical Verification expert with deep top-level DRC/LVS ownership experience on advanced nodes. The ideal candidate has led full-chip signoff worked closely with Physical Design Foundry and EDA teams and has strong command over Cadence Innovus and Siemens Calibre flows.

This role demands strong technical judgment debugging skills and the ability to drive closure on complex designs at 7nm / 5nm / 3nm and below.

Key Responsibilities

Own full-chip and block-level DRC/LVS signoff for advanced-node SoCs

Drive top-level DRC/LVS convergence using Calibre (nmDRC nmLVS RVE)

Integrate and debug Innovus Calibre signoff flows

Analyze debug and resolve complex DRC/LVS violations at top level

Work closely with Physical Design Timing Power and Packaging teams

Interface with Foundry (TSMC/Samsung/Intel) for rule interpretation and waivers

Develop and maintain runsets scripts and automation for signoff efficiency

Provide technical leadership and mentorship to junior engineers

Participate in tape-out execution and post-silicon debug support if required

Required Skills & Experience

10 years of hands-on experience in Physical Verification / Physical Design Signoff

Strong expertise in:

Calibre DRC LVS RVE

Cadence Innovus (top-level integration and signoff flows)

Proven experience owning full-chip/top-level DRC & LVS closure

Deep understanding of:

Advanced process nodes (7nm / 5nm / 3nm / 2nm)

Hierarchical and flat verification flows

Strong scripting skills in TCL / Perl / Python / Shell

Experience working with large complex SoCs (CPU/GPU/AI/Networking preferred)

Excellent debugging analytical and problem-solving skills

Principle Physical Verification Engineer Fulltime San Jose CA Role Overview We are looking for a hands-on Physical Verification expert with deep top-level DRC/LVS ownership experience on advanced nodes. The ideal candidate has led full-chip signoff worked closely with Physical Design Foundry and E...