Design Verification Engineer

Bengaluru - India

Monthly Salary: Not Disclosed

Posted on: Yesterday

Vacancies: 1 Vacancy

Job Summary

Job Title: Design Verification Engineer (UVM/SoC) Role Summary

We are seeking a detail-oriented Design Verification Engineer to join our hardware engineering team. You will be responsible for the full functional verification lifecycle of complex IP blocks and SoCs. Your primary focus will be building robust scalable UVM-based environments to ensure our silicon is first-time-right.

Key Responsibilities

Testbench Architecture: Develop and maintain sophisticated UVM-based testbenches and reusable verification components including drivers monitors agents and scoreboards.
Strategic Planning: Create and execute detailed verification plans by analyzing design specifications and architecture documents.
Test Generation: Write a mix of directed and constrained-random test cases to maximize functional correctness.
Debug & Analysis: Root-cause simulation failures using waveforms (e.g. Verdi/SimVision) and log files collaborating closely with RTL designers to resolve issues.
Coverage Closure: Define and achieve functional and code coverage goals; perform detailed analysis of coverage holes to ensure verification completeness.
Infrastructure: Utilize industry-standard EDA tools for simulation coverage analysis and managing large-scale regression runs.
IP/SoC Integration: Contribute to complex SoC verification projects ensuring protocol compliance (e.g. AXI AHB PCIe) and rigorous interface testing.
Collaboration: Actively participate in code reviews sprint planning and internal knowledge-sharing sessions.

Required Skills & Qualifications

Languages: Expert-level proficiency in SystemVerilog and UVM. Scripting experience with Python Perl or Tcl.
Methodology: Deep understanding of Constrained Random Verification (CRV) and Assertion-Based Verification (ABV).
Tools: Experience with major EDA simulators (VCS Questa or Xcelium).
Protocols: Familiarity with high-speed interfaces and bus protocols.
Education: B.S./M.S. in Electrical Engineering Computer Engineering or a related field.
Experience: Insert Range e.g. 3 7 years of experience in ASIC/FPGA verification.

Preferred Attributes

Strong analytical and problem-solving skills.
Ability to work effectively in a cross-functional fast-paced environment.
Experience with formal verification or power-aware (UPF) simulation is a plus.

Job Title: Design Verification Engineer (UVM/SoC) Role Summary We are seeking a detail-oriented Design Verification Engineer to join our hardware engineering team. You will be responsible for the full functional verification lifecycle of complex IP blocks and SoCs. Your primary focus will be buildin...

Job Title: Design Verification Engineer (UVM/SoC) Role Summary

Key Responsibilities

Testbench Architecture: Develop and maintain sophisticated UVM-based testbenches and reusable verification components including drivers monitors agents and scoreboards.
Strategic Planning: Create and execute detailed verification plans by analyzing design specifications and architecture documents.
Test Generation: Write a mix of directed and constrained-random test cases to maximize functional correctness.
Debug & Analysis: Root-cause simulation failures using waveforms (e.g. Verdi/SimVision) and log files collaborating closely with RTL designers to resolve issues.
Coverage Closure: Define and achieve functional and code coverage goals; perform detailed analysis of coverage holes to ensure verification completeness.
Infrastructure: Utilize industry-standard EDA tools for simulation coverage analysis and managing large-scale regression runs.
IP/SoC Integration: Contribute to complex SoC verification projects ensuring protocol compliance (e.g. AXI AHB PCIe) and rigorous interface testing.
Collaboration: Actively participate in code reviews sprint planning and internal knowledge-sharing sessions.

Required Skills & Qualifications

Languages: Expert-level proficiency in SystemVerilog and UVM. Scripting experience with Python Perl or Tcl.
Methodology: Deep understanding of Constrained Random Verification (CRV) and Assertion-Based Verification (ABV).
Tools: Experience with major EDA simulators (VCS Questa or Xcelium).
Protocols: Familiarity with high-speed interfaces and bus protocols.
Education: B.S./M.S. in Electrical Engineering Computer Engineering or a related field.
Experience: Insert Range e.g. 3 7 years of experience in ASIC/FPGA verification.