SoC Design for Test Engineer MCU
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Job Location:
Monthly Salary:
Posted on:
15 hours ago
Vacancies:
1 Vacancy
Job Summary
NXPs Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXPs advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence enabling applications across the autonomous home industrial automation and personal electronics
NXP is building new teams in Catania to create high impact microcontrollers (MCU) as part of NXPs intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class products at a world class pace.
This team will include all key engineering disciplines in Design Architecture Verification DfT and Physical Design to produce high performance and quality products.
We are now hiring for an SoCDfTEngineer:
SoCDfTEngineer isresponsiblefor designing implementing and verifying DFT architectures for complex SoCs.
You will work closely with RTL physical design and verification teams to ensure robust testability and high-quality silicon.
Role will also include working closely with Test Engineers torealizecost-effectiveandhigh-qualityproducts.
Job Responsibility:
Define and implement DFT architecture for SoCs (scan MBIST LBIST boundary scan).
Develop and integrate scan insertion test compression and ATPG patterns.
Implement memory BIST and logic BIST strategies.
Collaborate with RTL and physical design teams for DFT insertion and timing closure.
Perform DFT verification at RTL and gate-level simulations.
Work with ATE teams for test program development and silicon bring-up.
Optimize test coverage pattern count and test time.
Your Profile:
Masters degree inElectical/Electronics Engineering.
Strongexpertisein DFT methodologies: Scan MBIST LBIST JTAG.
Hands-on experience with industry standard ATPG tools.
Proficiencyin UPF/CPF-based low-power DFT.
Knowledge of fault models (stuck-at transition path delay).
Familiarity with physical design constraints for DFT.
Experience in silicon debug and ATE bring-up.
Past experiencewith SoC level DFT.
Exposure to high-speed interfaces and DFT for mixed-signal blocks.
Strong problem-solving and communication skills.
Commitment At NXP.
Werecognizewe can be a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. Weremainsteadfast in our commitment to sustainability and making measurable year-on-year progress. Also we aim to create an inclusive workenvironmentand we will not tolerate racismdiscriminationor harassment of any kind. We have programs in place focused on diversityinclusionand equality.
Required Experience:
IC
Key Skills
- Apache Commons
- Asset
- Art And Craft
- Concrete Pump
- Accident Investigation
About Company
NXP is a global semiconductor company creating solutions that enable secure connections for a smarter world.
