Senior SoC RTL Design Engineer (remote)
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Job Location:
Fayetteville, GA - USA
Monthly Salary:
Not Disclosed
Posted on:
9 hours ago
Vacancies:
1 Vacancy
Job Summary
Senior RTL Design Engineer
Remote / work from any US location
MUST be a US Citizen or US Permanent Resident
Full-time/employee Bonus Benefits 401k Stock Options etc
Responsibilities:
Assist with silicon bring-up
Design implement and integrate complex SoC blocks
Develop block-level test cases to deliver fully functional designs
Develop micro-architecture specifications based on the SoC requirements
Develop synthesis constraints and resolve timing issues
Identify and resolve RTL and GLS failures at block and chip level
Participate in architectural feasibility studies
Participate in ECO implementation
Resolve Lint CDC and DFT related issues
Required Skills & Experience:
BSEE/MSEE with 10 years of SoC design/architecture experience
Asynchronous logic design is a plus
Clock domain crossing methodologies
Experience with RISC-V architecture
Logic synthesis and static timing analysis
Modeling SoC architectures with FPGAs
RTL Design including HVLs and HDLs (SystemVerilog Verilog)
Scripting languages such as Python Perl Tcl shell etc.
SoC design flow including chip-level design block/IP design and behavioral modeling
Strong familiarity with EDA tools
Strong problem solving and debugging capabilities
Third Party IP Integration experience
Working knowledge of PCIe and DDR
Working knowledge of SoC design with CHISEL is a plus
Working knowledge of standard bus protocols such as AXI/AMBA/TileLink
#RTL #RTLDesign #SoC
Remote / work from any US location
MUST be a US Citizen or US Permanent Resident
Full-time/employee Bonus Benefits 401k Stock Options etc
Responsibilities:
Assist with silicon bring-up
Design implement and integrate complex SoC blocks
Develop block-level test cases to deliver fully functional designs
Develop micro-architecture specifications based on the SoC requirements
Develop synthesis constraints and resolve timing issues
Identify and resolve RTL and GLS failures at block and chip level
Participate in architectural feasibility studies
Participate in ECO implementation
Resolve Lint CDC and DFT related issues
Required Skills & Experience:
BSEE/MSEE with 10 years of SoC design/architecture experience
Asynchronous logic design is a plus
Clock domain crossing methodologies
Experience with RISC-V architecture
Logic synthesis and static timing analysis
Modeling SoC architectures with FPGAs
RTL Design including HVLs and HDLs (SystemVerilog Verilog)
Scripting languages such as Python Perl Tcl shell etc.
SoC design flow including chip-level design block/IP design and behavioral modeling
Strong familiarity with EDA tools
Strong problem solving and debugging capabilities
Third Party IP Integration experience
Working knowledge of PCIe and DDR
Working knowledge of SoC design with CHISEL is a plus
Working knowledge of standard bus protocols such as AXI/AMBA/TileLink
#RTL #RTLDesign #SoC
Required Experience:
Senior IC
Key Skills
- Aerospace Engineering
- Anti Money Laundering
- Electrical Installation
- Desktop Support
- Corporate Marketing
- Fabrication
