Senior ASIC Design Verification Engineer
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Job Location:
Minneapolis, MN - USA
Monthly Salary:
Not Disclosed
Posted on:
4 days ago
Vacancies:
1 Vacancy
Job Summary
ASIC Design Verification Engineer
Must be a US Citizen
Full-Time Health Benefits 401K Plan with profit sharing PTO Stock Option Plan
Duties and Responsibilities:
Reviewing and editing target specifications as required for completeness and feasibility
Developing architectures and specifications for complex design blocks and SOCs
Implementing complex digital designs using reusable RTL methods (Verilog VHDL SystemVerilog)
Complex computational architectures and algorithms such as multi-rate/DSP and µP design
Modern verification methods including directed/constrained-random stimuli assertions TLM and UVM
Collaborative creation of comprehensive verification plans and coverage metrics
Multi-supply-domain and UPF methods
Constraining and synthesizing digital designs to target cell libraries
Static timing power and SI analyses of complex digital designs
Supporting place & route efforts including P/G and floorplanning timing and physical constraints gated CTS MCMM setups back-annotation timing closure equivalence checking
Planning implementing and analyzing designs for DFT test hooks and scan/ATPG/JTAG/BIST and supporting production test with ATE patterns (ATPG and functional) and timeset definitions
Proficiency with Synopsys EDA including DC-Topo VCS-MX PrimeTime Formality TetraMAX
Proficiency with Mentor EDA including Questa ADMS Tessent
Modern revision-control tools and best-practices in a collaborative multi-site design community
Proficiency with UNIX/Linux including shell scripting text utilities (e.g. sed awk grep) using Modules high-level programming such as C/C PERL/Python/TCL scripting
Proficiency with Windows apps including Word Excel PowerPoint Visio Project PDF conversion
Requirements:
BSEE/MSEE or BSCS/MSCS or equivalent
7 years of direct industry experience with ASIC and/or SoC design
A strong background in RTL based digital IC design using Verilog/SystemVerilog
Proven track record of first-pass successes
Self-starter with the ability to assume leadership roles
Ability to work well in a diverse team environment
Willingness to mentor junior engineers
Experience with industry standard development tools and methodologies
DESIGN VERIFICATION GROUP on LinkedIn: Leon
Talent Acquisition
Chelsea Search Group
cell
(are we connected)
Must be a US Citizen
Full-Time Health Benefits 401K Plan with profit sharing PTO Stock Option Plan
Duties and Responsibilities:
Reviewing and editing target specifications as required for completeness and feasibility
Developing architectures and specifications for complex design blocks and SOCs
Implementing complex digital designs using reusable RTL methods (Verilog VHDL SystemVerilog)
Complex computational architectures and algorithms such as multi-rate/DSP and µP design
Modern verification methods including directed/constrained-random stimuli assertions TLM and UVM
Collaborative creation of comprehensive verification plans and coverage metrics
Multi-supply-domain and UPF methods
Constraining and synthesizing digital designs to target cell libraries
Static timing power and SI analyses of complex digital designs
Supporting place & route efforts including P/G and floorplanning timing and physical constraints gated CTS MCMM setups back-annotation timing closure equivalence checking
Planning implementing and analyzing designs for DFT test hooks and scan/ATPG/JTAG/BIST and supporting production test with ATE patterns (ATPG and functional) and timeset definitions
Proficiency with Synopsys EDA including DC-Topo VCS-MX PrimeTime Formality TetraMAX
Proficiency with Mentor EDA including Questa ADMS Tessent
Modern revision-control tools and best-practices in a collaborative multi-site design community
Proficiency with UNIX/Linux including shell scripting text utilities (e.g. sed awk grep) using Modules high-level programming such as C/C PERL/Python/TCL scripting
Proficiency with Windows apps including Word Excel PowerPoint Visio Project PDF conversion
Requirements:
BSEE/MSEE or BSCS/MSCS or equivalent
7 years of direct industry experience with ASIC and/or SoC design
A strong background in RTL based digital IC design using Verilog/SystemVerilog
Proven track record of first-pass successes
Self-starter with the ability to assume leadership roles
Ability to work well in a diverse team environment
Willingness to mentor junior engineers
Experience with industry standard development tools and methodologies
DESIGN VERIFICATION GROUP on LinkedIn: Leon
Talent Acquisition
Chelsea Search Group
cell
(are we connected)
Required Experience:
Senior IC
Key Skills
- Arabic Speaking
- Logistics Operations
- Lecturing
- Community Support
- Gynaecology & Obstetrics
- AC Maintenance
