Senior FPGA Engineer

Looking for an opportunity to make an impact

At Leidos we deliver innovative solutions through the efforts of our diverse and talented people who are dedicated to our customers success. We empower our teams contribute to our communities and operate sustainably. Everything we do is built on a commitment to do the right thing for our customers our people and our community. Our Mission Vision and Values guide the way we do business.

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Leidos Defense Sector Space Business Area is seeking a SeniorFPGA Engineer to join our team in San Diego CA. This is an exciting opportunity to leverage your expertise in successfully deploying complex engineering projects while contributing to our national defense mission.

We are looking for engineers who thrive in fast-paced environments and have a passion for developing and delivering high-tech solutions. Experience in space qualified designs for LEO MEO and GEO will be a plus and we value and welcome those with experience working for organizations like SDA RCO or DARPA. Emphasis is on complete life-cycle development of complex FPGAs starting with architecture design implementation timing closure and hardware testing.

If this sounds like the kind of environment where you can thrive keep reading!

Leidos Defense Sector provides a diverse portfolio of systems solutions and services covering land sea air space and cyberspace for customers worldwide. Solutions for Defense include enterprise and mission IT large-scale intelligence systems command and control geospatial and data analytics cybersecurity logistics training and intelligence analysis and operations support. Our team is solving the worlds toughest security challenges for customers with cant fail missions. To explore and learn more click here!

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THE CHALLENGE (primary responsibilities)

• Complete ownership to architect the full high-density FPGA level design develop/code/test the design and finally integrate it on the hardware

• Mentor junior FPGA engineers as needed

• Perform data analysis write technical reports perform internal and customer design reviews write and maintain interface design documents for complex FPGA design

• Develop and test FPGA designs for Chemical Biological Radiation Nuclear and Space sensor systems for federal government customers.

• Develop and execute FPGA test plans determine root cause of test failures and iterate with senior staff to determine design changes to improve FPGA performance.

• Collaborate with a multi-disciplined design team to design and integrate DSP applications for latest System on a Chip (SoC) implementations such as Xilinx Zynq Ultrascale and Xilinx Versal

• Understanding of image processing algorithms basic knowledge of digital signal processing and tools to implement the DSP algorithms on the FPGA.

• Analyze design and implement HDL test benches in hardware description languages HDL (VHDL SystemVerilog) for code validation and validation against models.

• Ensure designs synthesize place and route meeting timing requirements from Virtex/Kintex7 PolarFire and Versal FPGAs.

• Implement common signaling standards typical IP hard macros such as SERDES PLLS etc. and/or protocols such PCIe Gen4 40GBE Ethernet DDR3/4 etc.

• Use judgment to perform technical troubleshooting and diagnosis of failed equipment and support root cause analysis.

• 0-10% travel to customer sites as required.

WHAT SETS YOU APART (basic qualifications)

• Proven ability to architect the entire FPGA level design develop/code/test the design and finally integrate it on the hardware is a must for this position.

• Bachelors degree with 12 years relevant experience or M.S. degree in Electrical Engineering Computer Engineering or related field from an accredited college/university with 10 years of relevant experience as an electrical engineer or computer engineer

• Must be able to obtain and maintain a Top Secret Security Clearance.

• Fluent in Vivado Modelsim or Riviera. Fluent in testbenches and self-checking verification methods. Must be able to synthesize place and route meet high-speed timing closure for Xilinx FPGAs.

• Current hands-on experience in HDL design simulation and testing a must

• Working knowledge of electronics test equipment like function generators oscilloscopes logic analyzers and lab power supplies.

• Well-organized reliable attention to detail demonstrated personal initiative. Ability to multi-task and prioritize workload. Good interpersonal skills and ability to coordinate work with others. Good oral and written communication skills.

• Motivated self-starter able to work under minimal supervision and an entrepreneurial approach to roles and responsibilities.

• Familiarity with GIT JIRA Agile Scrum

Preferred Qualifications

• Masters degree or higher in Electrical/Computer Engineering with emphasis on digital/ASIC/FPGA design is a plus.

• Breadth of experience in a complementary discipline ability to develop image processing algorithms in Matlab and implement them in HDL FPGA design or embedded software is a plus.

• Experience with Microchip Polarfire and Libero tools is a plus

• Experience reviewing and documenting technical data packages for military products.

• Demonstrated senior-level lead position in a large FPGA project

• Active Clearance

If youre looking for comfort keep scrolling. At Leidos we outthink outbuild and outpace the status quo because the mission demands it. Were not hiring followers. Were recruiting the ones who disrupt provoke and refuse to fail. Step 10 is ancient history. Were already at step 30 and moving faster than anyone else dares.

Original Posting:

Pay Range:

The Leidos pay range for this job level is a general guideline onlyand not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job education experience knowledge skills and abilities as well as internal equity alignment with market data applicable bargaining agreement (if any) or other law.