Axiado Corporation is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup environment. This role is designed for a senior technologist who combines deep hands-on expertise with system-level thinking and who thrives in high-ambiguity high-impact settings.
You will define and drive high-performance low-power packaging architectures spanning 2D and RDL based fan-out (2.5D) chiplet-based designs and heterogeneous integration leading efforts from early technology path finding through production ramp. You will work closely with foundries OSATs substrate suppliers and internal cross-functional teams to shape both product execution and long-term packaging strategy.
Key Responsibilities
- Serve as technical authority for IC and SiP packaging across multiple products and programs.
- Own package architecture and technology roadmap aligned with product cost and scalability goals.
- Lead chiplet-based packaging strategies including UCIe silicon interposers and advanced RDL.
- Perform and guide hands-on package design and physical layout including critical structures for High-speed SerDes/PHY (PCIe CXL) LPDDR5 UCIe and Other multi-gigabit interfaces.
- Define substrate stack-ups materials bump/RDL architectures and DFM guidelines for advanced nodes.
- Drive SI/PI thermal mechanical and reliability trade-offs at the system and package levels.
- Lead external engagement with OSATs foundries and key suppliers for technology development and manufacturing readiness.
- Influence product roadmap risk management and investment decisions through technical insight.
- Establish scalable design methodologies best practices and reusable packaging flows.
Qualifications :
Required Experience
- Technical leadership of multiple end-to-end packaging programs from early architecture through high-volume production.
- Proven experience with high-speed SerDes package development including PCIe Gen5 LPDDR5 / LPDDR5X USB 3.x or 10G interfaces
- Experience defining die-to-die and chiplet based RDL/bump architecture.
- Direct collaboration with OSATs foundries and substrate suppliers for co-development and ramp.
- Strong cross-functional leadership across design product test operations reliability and customer teams.
- Clear understanding of cost yield schedule and risk trade-offs at a product and portfolio level.
Tools & Preferred Skills
- Cadence Allegro Package Designer (APD) or equivalent EDA tools.
- Strong background in flip-chip BGA package design and layout.
- SI/PI expertise preferred including S-parameter extraction and PDN optimization using HFSS SIwave or Ansys Designer.
- Experience building new packaging methodologies or platforms from scratch.
Additional Information :
Axiado is committed to attracting developing and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley with access to the worlds leading research technology and talent.
We are building an exceptional team to secure every node on the internet. For us solving real-world problems takes precedence over purely theoretical problems. As a result we prefer individuals with persistence intelligence and high curiosity over pedigree alone. Working hard and smart continuous learning and mutual support are all part of who we are.
Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race religion color sex gender identity sexual orientation age non-disqualifying physical or mental disability national origin veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications merit and business need.
Remote Work :
No
Employment Type :
Full-time
Axiado Corporation is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup environment. This role is designed for a senior technologist who combines deep hands-on expertise with system-l...
Axiado Corporation is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup environment. This role is designed for a senior technologist who combines deep hands-on expertise with system-level thinking and who thrives in high-ambiguity high-impact settings.
You will define and drive high-performance low-power packaging architectures spanning 2D and RDL based fan-out (2.5D) chiplet-based designs and heterogeneous integration leading efforts from early technology path finding through production ramp. You will work closely with foundries OSATs substrate suppliers and internal cross-functional teams to shape both product execution and long-term packaging strategy.
Key Responsibilities
- Serve as technical authority for IC and SiP packaging across multiple products and programs.
- Own package architecture and technology roadmap aligned with product cost and scalability goals.
- Lead chiplet-based packaging strategies including UCIe silicon interposers and advanced RDL.
- Perform and guide hands-on package design and physical layout including critical structures for High-speed SerDes/PHY (PCIe CXL) LPDDR5 UCIe and Other multi-gigabit interfaces.
- Define substrate stack-ups materials bump/RDL architectures and DFM guidelines for advanced nodes.
- Drive SI/PI thermal mechanical and reliability trade-offs at the system and package levels.
- Lead external engagement with OSATs foundries and key suppliers for technology development and manufacturing readiness.
- Influence product roadmap risk management and investment decisions through technical insight.
- Establish scalable design methodologies best practices and reusable packaging flows.
Qualifications :
Required Experience
- Technical leadership of multiple end-to-end packaging programs from early architecture through high-volume production.
- Proven experience with high-speed SerDes package development including PCIe Gen5 LPDDR5 / LPDDR5X USB 3.x or 10G interfaces
- Experience defining die-to-die and chiplet based RDL/bump architecture.
- Direct collaboration with OSATs foundries and substrate suppliers for co-development and ramp.
- Strong cross-functional leadership across design product test operations reliability and customer teams.
- Clear understanding of cost yield schedule and risk trade-offs at a product and portfolio level.
Tools & Preferred Skills
- Cadence Allegro Package Designer (APD) or equivalent EDA tools.
- Strong background in flip-chip BGA package design and layout.
- SI/PI expertise preferred including S-parameter extraction and PDN optimization using HFSS SIwave or Ansys Designer.
- Experience building new packaging methodologies or platforms from scratch.
Additional Information :
Axiado is committed to attracting developing and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley with access to the worlds leading research technology and talent.
We are building an exceptional team to secure every node on the internet. For us solving real-world problems takes precedence over purely theoretical problems. As a result we prefer individuals with persistence intelligence and high curiosity over pedigree alone. Working hard and smart continuous learning and mutual support are all part of who we are.
Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race religion color sex gender identity sexual orientation age non-disqualifying physical or mental disability national origin veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications merit and business need.
Remote Work :
No
Employment Type :
Full-time
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