Principal Engineer Memory Compiler Circuit Design

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

Essential Skills & Qualifications

• Technical:Custom memory circuit design (sense amps periphery) analog/digital CMOS semiconductor physics DFT Verilog/VHDL scripting (Perl/Python/TCL).
• Tools:Cadence Virtuoso Synopsys tools (Design Compiler PrimeTime) HSPICE Spectre solido.
• Experience:Deep sub-micron nodes (7nm/5nm/3nm) compiler IP development foundry PDKs memory characterization.
• Education:BSEE or related technical degree (MSEE often preferred).

Role Significance

• Strategic Impact:Influences cross-team strategy and technical direction beyond just project leadership.

What Were Looking For

• Architect & Design:Develop high-performance low-power memory IP (SRAM Register Files) and compiler architectures. Expect the individual to be innovative to innovate on new circuit ideas and architectures. Expect the individual to have done and lead development of all kinds of memory compilers such as 1R1W SRAM 2R2W ROM etc Expect the individual to be well versed in all aspects of memory compiler design such as circuit design of all sub blocks of memories critical path block wise design validation of all blocks (Sense bitcell Rowdec level shifter etc..) Memory level design validation such as self time analysis Montecarlo analysis race check analysis etc Expect the individual to be also aware of characterization methodology and process. Expect the individual to be well aware of all deliverables of memory compiler.
• PPAOptimization:Drive design methodologies for power performance and area targets Push the designs to achieve the maximum PPA targets.
• Leading Edge Process-Design co-optimization for Robust design:Expect the individual to have worked on leading edge nodes like 2nm 3nm etc and on GAE Finfet & planar. Expect the individual to understand all the process complexities and build robust compilers
• Automation:Enhance compiler flows generators and design libraries using scripting (Python TCL).
• Mentorship:Guide junior engineers in circuit design and best practices.
• Collaboration:Work across teams (logic architecture layout characterization test) and with foundries/vendors.
• Technical Leadership:Define technical direction review designs and ensure tape-out readiness.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.