Verification Engineer (RTL design verification)

Austin, TX - USA

Monthly Salary: Not Disclosed

Posted on: 13 hours ago

Vacancies: 1 Vacancy

Job Summary

We are currently hiring for a Verification Engineer role with a cutting-edge technology company working on next-generation optical communication systems (800G 1.6T and beyond). This is a full-time onsite position in Austin TX offering strong technical ownership long-term growth and an equity component.

About the Role

As a Verification Engineer you will be deeply involved in RTL design verification across complex digital blocks. You will collaborate closely with design and architecture teams and play a key role in ensuring full functional coverage and sign-off for advanced silicon platforms that enable AI-driven data infrastructure.

Key Responsibilities

Plan architect and execute verification strategies based on design specifications
Develop and maintain verification environments using SystemVerilog and UVM
Define and implement functional code and corner-case coverage
Debug RTL functionality and collaborate with cross-functional teams
Perform coverage analysis and drive coverage closure
Participate in design reviews test plan creation regressions and verification sign-off

Required Qualifications (Must-Have)

5 years of professional experience in digital/RTL engineering
3 years of hands-on design verification experience
Strong expertise in VLSI verification flows concepts and industry-standard tools
Proven completion of at least one full block or system-level verification cycle
Hands-on experience with SystemVerilog UVM (or equivalent frameworks such as Specman/eRM or SystemC)
Excellent debugging skills and familiarity with waveform analysis tools
Onsite availability in Austin TX five days per week (mandatory)

Nice to Have

Digital datapath or protocol-level verification (Ethernet or high-speed interfaces preferred)
Advanced functional code and corner-case coverage experience
Exposure to mixed-signal or analog/digital verification environments
Strong written and verbal communication skills

Additional Details

Location: Austin TX (Onsite 5 days/week)
Interview Process: 3 rounds (approximately 2 weeks)
Visa: H1-B sponsorship available
Equity: Yes (4-year vesting; details discussed during later stages)
Benefits: Full Medical Dental and Vision coverage
Relocation: Available (case dependent)

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We are currently hiring for a Verification Engineer role with a cutting-edge technology company working on next-generation optical communication systems (800G 1.6T and beyond). This is a full-time onsite position in Austin TX offering strong technical ownership long-term growth and an equity compone...

About the Role

Key Responsibilities

Plan architect and execute verification strategies based on design specifications
Develop and maintain verification environments using SystemVerilog and UVM
Define and implement functional code and corner-case coverage
Debug RTL functionality and collaborate with cross-functional teams
Perform coverage analysis and drive coverage closure
Participate in design reviews test plan creation regressions and verification sign-off

Required Qualifications (Must-Have)

5 years of professional experience in digital/RTL engineering
3 years of hands-on design verification experience
Strong expertise in VLSI verification flows concepts and industry-standard tools
Proven completion of at least one full block or system-level verification cycle
Hands-on experience with SystemVerilog UVM (or equivalent frameworks such as Specman/eRM or SystemC)
Excellent debugging skills and familiarity with waveform analysis tools
Onsite availability in Austin TX five days per week (mandatory)

Nice to Have

Digital datapath or protocol-level verification (Ethernet or high-speed interfaces preferred)
Advanced functional code and corner-case coverage experience
Exposure to mixed-signal or analog/digital verification environments
Strong written and verbal communication skills

Additional Details