At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
About Us
Cadence is a pivotal leader in electronic design building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software hardware and IP that turn design concepts into reality. This strategy is supplemented by AI-augmented development practices throughout all our organizations to empower our team to focus on creative problem-solving and innovation. Our customers are the worlds most innovative companies delivering extraordinary electronic productsfrom chips to boards to systemsfor dynamic market applications including consumer hyperscale computing 5G communications automotive aerospace industrial and health. Join us and be part of a culture that values innovation collaboration and customer success.
Position Overview
We invite you to join a growing and innovative IP team dedicated to building best-in-class digital and mixed-signal IP solutions. You will work alongside seasoned professionals developing high-performance IP across protocols such as this role you will be integral to the organizations efforts to support post-silicon bring-up for customers.
Key Responsibilities
- Lead bringup and debug of CDNS SerDes PHY IPs for customer silicon.
- Perform detailed analysis of signal integrity jitter and BER performance.
- Drive rootcause investigations for silicon issues and propose corrective actions.
- Use oscilloscopes BERTs protocol analyzers and other lab equipment to measure CDNS PHY function and performance. Maintain CDNS Testchip bench locally to duplicate and debug the issues that external customers are dealing with.
- Collaborate with FW teams to validate SerDes initialization sequences support FW debugging related to SerDes bringup.
- Working with global (US west and east coast) teams in different time-zones.
- Travel as needed to support postsilicon bringup and customer engagements.
- AI Incorporation: Leverage AI-powered tools and assistants to enhance productivity improve decision making and maintain high-quality customer deliverables. Apply AI-powered analytics tools to extract insights identify patterns and generate actionable recommendations from complex datasets.
Skills & Qualifications
Required
- Bachelors in computer science or electrical engineering 7 years of related experience or Masters 5 years of related experience.
- Very strong experience in silicon bring-up with lab equipment (Scope/Bert/PCIe exerciser/analyzer)
- Very strong experience in PCIe protocol PCIe LTSSM link stable analysis PCI Compliance test.
- Familiar with board design. Ability to read schematics and conduct SI/PI analysis and review for customer board implementation.
- Strong communication and organizational skills.
- Ability to prioritize cases anticipate escalations
- Experience on Ethernet or USB or DP or JESD will be plus.
- Experience on Serdes components like Tx FFE Rx CTLE& DFE& VGA&FFE will be plus.
- Experience on DSP based Serdes receiver will be plus.
- Experience on PLL algorithm will be plus.
Were doing work that matters. Help us solve what others cant.
Required Experience:
Staff IC
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.About UsCadence is a pivotal leader in electronic design building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver softwa...
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
About Us
Cadence is a pivotal leader in electronic design building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software hardware and IP that turn design concepts into reality. This strategy is supplemented by AI-augmented development practices throughout all our organizations to empower our team to focus on creative problem-solving and innovation. Our customers are the worlds most innovative companies delivering extraordinary electronic productsfrom chips to boards to systemsfor dynamic market applications including consumer hyperscale computing 5G communications automotive aerospace industrial and health. Join us and be part of a culture that values innovation collaboration and customer success.
Position Overview
We invite you to join a growing and innovative IP team dedicated to building best-in-class digital and mixed-signal IP solutions. You will work alongside seasoned professionals developing high-performance IP across protocols such as this role you will be integral to the organizations efforts to support post-silicon bring-up for customers.
Key Responsibilities
- Lead bringup and debug of CDNS SerDes PHY IPs for customer silicon.
- Perform detailed analysis of signal integrity jitter and BER performance.
- Drive rootcause investigations for silicon issues and propose corrective actions.
- Use oscilloscopes BERTs protocol analyzers and other lab equipment to measure CDNS PHY function and performance. Maintain CDNS Testchip bench locally to duplicate and debug the issues that external customers are dealing with.
- Collaborate with FW teams to validate SerDes initialization sequences support FW debugging related to SerDes bringup.
- Working with global (US west and east coast) teams in different time-zones.
- Travel as needed to support postsilicon bringup and customer engagements.
- AI Incorporation: Leverage AI-powered tools and assistants to enhance productivity improve decision making and maintain high-quality customer deliverables. Apply AI-powered analytics tools to extract insights identify patterns and generate actionable recommendations from complex datasets.
Skills & Qualifications
Required
- Bachelors in computer science or electrical engineering 7 years of related experience or Masters 5 years of related experience.
- Very strong experience in silicon bring-up with lab equipment (Scope/Bert/PCIe exerciser/analyzer)
- Very strong experience in PCIe protocol PCIe LTSSM link stable analysis PCI Compliance test.
- Familiar with board design. Ability to read schematics and conduct SI/PI analysis and review for customer board implementation.
- Strong communication and organizational skills.
- Ability to prioritize cases anticipate escalations
- Experience on Ethernet or USB or DP or JESD will be plus.
- Experience on Serdes components like Tx FFE Rx CTLE& DFE& VGA&FFE will be plus.
- Experience on DSP based Serdes receiver will be plus.
- Experience on PLL algorithm will be plus.
Were doing work that matters. Help us solve what others cant.
Required Experience:
Staff IC
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