Senior Staff Physical Design Manager

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Provide technical direction coaching and mentoring to employees on your team and others when necessary to achieve successful project outcomes

• Assist in planning and designating project resources monitor progress and keep stakeholders informed the entire way

• Partner with other ASIC design teams to ensure project success

• Possibility of being management interface to ASIC customers

• Lead recruiting efforts at local universities and hiring of experienced engineers

What Were Looking For

• Bachelors degree in Computer Science Electrical Engineering or related fields and 5-10 years of related professional experience or Masters degree and/or PhD in Computer Science Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree

• Must have a background in ASIC or SOC development

• Physical design knowledge from netlist handoff to GDS tape-out including floor planning place and route clock tree synthesis timing closure and physical verification

• Must be able to handle a wide variety of projects and technical challenges

• Diligent detail-oriented and able to handle assignments with minimal supervision

• The successful candidate will have excellent written and oral communications skills and ability to collaborate and be effective in fast-paced environment

• Self-driven individual and with ability to partner with world-wide team

Preferred Qualifications:

• Minimum 2 years of experience leading projects within semiconductor product development or tape-out cycles. Proven track record of team mentorship for high performance.

• Technical leadership of ASIC or SOC Netlist to GDS tape-out

• Experience as either top-level physical design lead STA chip Lead or chip DFT lead

• Project management experience of ASIC or SOC

• Customer interface experience

• Experience working with a distributed team

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.