Senior Staff STA Engineer
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Job Location:
Monthly Salary:
Posted on:
30+ days ago
Vacancies:
1 Vacancy
Job Summary
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
This position is with Timing signoff team part of The Central Engineering PD group at Marvell Bangalore. This team is part of global Implementation team that plays a key role in Netlist to GDS implementation covering Synthesis P&R Timing PV and Power implementation all custom ASICs for all the OEMs. We are looking for a strong technical individual contributor having experience in STA using industry standard tools.What You Can Expect
- As a STA engineer you will be part of our signoff team responsible for signing off timing for the next generation Multi-Ghz high-performance processor SOC and custom ASIC chips in leading-edge CMOS process technology.
- Work with design teams across various disciplinessuch as Digital/RTL/Analog in helping them take their blocks (custom PnR) through the global timing flow and making sure all the blocks meet timing requirements.
- Be responsible for .constraint development validation at the block/subsystem/full chip level.
- Responsible for timing closure of sub systems/full chip across timing modes.
- Provide technical direction coaching and mentoring to employees on yourteam and others when necessary to achieve successful project outcomes.
- Writing scripts in TCL and Perl to achieve productivity enhancements through automation.
What Were Looking For
- B-Tech with 10 or M-Tech candidate with 8 years of hands-on experience and leadership in full-chip STA/Synthesis. Should have played a Timing lead role with 5 years experience in handling Timing sign off for multi-million hierarchical designs.
- Should have hands on constraints development experience including third party IPs budgeting STA modes understanding (FUNC/TEST) and driving the timing closure for block Subsystem as well as chip level.
- Driving the timing closure for block Subsystem as well as chip level.
- Candidate should have excellent problem solving skills in timing domain should be well versed with scripting language PERL/TCL/AWK/Shell .
- Candidate Should have experience in working with global teams as a timing lead handling Customer/Stakeholder interactions driving technical deliverables/dependencies across the design cycle (DFT/PD/FE/Power)
- Candidate should possess excellent inter-personal skills with experience in providing mentorship to junior engineers reviewing designs and providing technical guidance
Additional Compensation and Benefit Elements
With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Interview Integrity
As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.
#LI-MN1Required Experience:
Staff IC
Key Skills
- Computer Science
- Docker
- Kubernetes
- Python
- VMware
- C/C++
- Go
- System Architecture
- gRPC
- OS Kernels
- Perl
- Distributed Systems
About Company
Designed for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
