Overview:
TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories graphics processors motherboard chip sets and a variety of components used in consumer electronics goods.
Job Title: Design Verification Engineer
Work Location: Austin TX 78728
Duration: 12 Months
Work Type: Temporary Assignment
Job Type: Onsite
Job Description:
THE ROLE:
- We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification.
- You have had significant success driving IP verification UVM and SystemVerilog.
- This senior role will stretch you as you lead DV teams in new directions network with our world-class design/DV teams.
THE PERSON:
- You have excellent communication and presentation skills demonstrated through technical publications presentations trainings executive briefings etc.
- You are highly adept at collaboration among top-thinkers and engineers alike ready to mentor and guide and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES:
- Define verification plan and provide technical direction to execution teams
- Comprehend AMS Firmware and design spec. Work with other functional leads to come up with a DV plan and execute the plan.
- Create UVM/SystemVerilog based testbenches and tests.
- Make sure that design is bug free.
- Lead Formal verification.
- Support Post-Si teams for Product Performance Power and functional issues debug/resolution
PREFERRED EXPERIENCE:
- IO/PHY knowledge.
- Formal verification expertise.
- Firmware experience.
- Excellent communication management and presentation skills.
- Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in related discipline preferred
TOP MUST HAVE SKILLS:
- UVM SystemVerilog RTL verification
TekWissen Group is an equal opportunity employer supporting workforce diversity.
Overview: TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors...
Overview:
TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories graphics processors motherboard chip sets and a variety of components used in consumer electronics goods.
Job Title: Design Verification Engineer
Work Location: Austin TX 78728
Duration: 12 Months
Work Type: Temporary Assignment
Job Type: Onsite
Job Description:
THE ROLE:
- We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification.
- You have had significant success driving IP verification UVM and SystemVerilog.
- This senior role will stretch you as you lead DV teams in new directions network with our world-class design/DV teams.
THE PERSON:
- You have excellent communication and presentation skills demonstrated through technical publications presentations trainings executive briefings etc.
- You are highly adept at collaboration among top-thinkers and engineers alike ready to mentor and guide and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES:
- Define verification plan and provide technical direction to execution teams
- Comprehend AMS Firmware and design spec. Work with other functional leads to come up with a DV plan and execute the plan.
- Create UVM/SystemVerilog based testbenches and tests.
- Make sure that design is bug free.
- Lead Formal verification.
- Support Post-Si teams for Product Performance Power and functional issues debug/resolution
PREFERRED EXPERIENCE:
- IO/PHY knowledge.
- Formal verification expertise.
- Firmware experience.
- Excellent communication management and presentation skills.
- Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in related discipline preferred
TOP MUST HAVE SKILLS:
- UVM SystemVerilog RTL verification
TekWissen Group is an equal opportunity employer supporting workforce diversity.
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