IC Layout Designer (TSMC FinFET)

San Jose, CA - USA

Monthly Salary: Not Disclosed

Posted on: 15 days ago

Vacancies: 1 Vacancy

Job Summary

IC Layout Designer
Full-time Benefits
Remote from any US location
US Citizen or US Permanent Resident

Requirements:
3 years of experience in Cadence layout (Virtuoso VXL) and Calibre verification (ERC DRC LVS)
3 years of experience in layout and verification tools and methodologies for RF/Analog/Mixed-Signal ICs
BSEE or AA degree
TSMC FinFET experience in advanced technology nodes (7nm and below)
Comprehensive understanding of matching shielding guard rings and latch up
Debugging and analytical skills with complex technical concepts
Demonstrated success in delivering quality work product
Experience in DFM hierarchical layout construction for efficient verification and integration
Must understand techniques for managing layout dependent effects i.e. IR drop RC delay electron-migration self- heating and crosstalk
Proficiency in PERL or SKILL scripting is a plus
Strong verbal and written communication

IC MASK LAYOUT DESIGN GROUP on LinkedIn: Leon
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IC Layout DesignerFull-time BenefitsRemote from any US locationUS Citizen or US Permanent ResidentRequirements: 3 years of experience in Cadence layout (Virtuoso VXL) and Calibre verification (ERC DRC LVS) 3 years of experience in layout and verification tools and methodologies for RF/Analog/Mixed-...