IP Design Engineer

San Jose, CA - USA

Monthly Salary: Not Disclosed

Posted on: 16-10-2025

Vacancies: 1 Vacancy

Job Summary

Overview:

TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories graphics processors motherboard chip sets and a variety of components used in consumer electronics goods.

Job Title: IP Design Engineer

Work Location: San Jose CA

Duration: 6 Months

Work Type: Temporary Assignment

Job Type: Hybrid

Job Description:

We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of client-Xilinx FPGA Architecture.
In this role you will design Register-Transfer Level (RTL) Intellectual Property (IP) with a focus on video connectivity subsystems.
You will have dynamic multi-faceted responsibilities in areas such as project definition RTL design and implementation.
You will participate in the design architecture documentation and implementation of the low latency video connectivity systems.
You will be also responsible for RTL coding of blocks specified by you or others. Additionally you will be responsible for various front-end methodology flows that include resource optimization clock domain crossing and reset domain crossing.

Qualifications:

Must have proven experience working on Video domain IPs / Digital IPs.
Must have proven experience working of one or more of protocols at the IP level: MIPI CSI / MIPI DSI / DisplayPort /HDMI / SDI.
Hands on experience with client/Xilinx FPGA device and Vivado toolchain.
Hands on experience with architecting / micro-architecture / detailed design from functional specifications.
Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for FPGA designs.
Lint CDC synthesis flow and static timing flows formal checking etc. experience.
Working knowledge / experience TCL Perl Python is an added advantage.
SERDES architecture knowledge is a plus.
Has a solid desire to learn and explore new technologies.
Strong communication and presentation skills.
Close collaboration with different teams across various time zones.

MUST HAVE SKILLS:

Direct Experience with RTL IP Design using Verilog/Systemverilog.
Must have proven experience working on Video domain IPs / Digital IPs
Must have proven experience working of one or more of protocols at the IP level: MIPI CSI / MIPI DSI / DisplayPort /HDMI / SDI.

TekWissen Group is an equal opportunity employer supporting workforce diversity.

Overview: TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors...