Work as a specialized SOC clock implementation engineer and manage a team of clock design
engineers. Use engineering skills to define clock methodology for System on Chip including clock
structure simulation model and physical implementation for high performance low power CPU
cluster Memory modules and subsystems. Develop and maintain an efficient clock structure with
low latency and skew. Analyze clock tree quality and provide guidance to improve quality. Engage
with the SOC physical design team on the adoption of the clock methodology for high
performance designs. Work with synthesis place & route STA Spice and other related
analysis/verification tools for electrical engineering and design. Help engineer the CMOS circuit
focusing on low power design electromigration (EM) voltage droop (IR) noise design-for-
manufacturing (DFM) and other related engineering design challenges.
Education:
- Masters or foreign equivalent in Electrical Engineering or related field
Experience:
- 7 years of experience in job offered or related occupation.
Special Requirements: Must have at least 1 year of prior work experience in each of the following
Worksite:
- 6433 Champion Grandview Way Building 2 Suite 150 Austin Texas 78750
Applicant Instructions:
- Email resume to:
- Include job code 91498 in reply. EOE.
We may use artificial intelligence (AI) tools to support parts of the hiring process such as reviewing applications analyzing resumes or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed please contact us.
Required Experience:
Staff IC
Work as a specialized SOC clock implementation engineer and manage a team of clock designengineers. Use engineering skills to define clock methodology for System on Chip including clockstructure simulation model and physical implementation for high performance low power CPUcluster Memory modules and...
Work as a specialized SOC clock implementation engineer and manage a team of clock design
engineers. Use engineering skills to define clock methodology for System on Chip including clock
structure simulation model and physical implementation for high performance low power CPU
cluster Memory modules and subsystems. Develop and maintain an efficient clock structure with
low latency and skew. Analyze clock tree quality and provide guidance to improve quality. Engage
with the SOC physical design team on the adoption of the clock methodology for high
performance designs. Work with synthesis place & route STA Spice and other related
analysis/verification tools for electrical engineering and design. Help engineer the CMOS circuit
focusing on low power design electromigration (EM) voltage droop (IR) noise design-for-
manufacturing (DFM) and other related engineering design challenges.
Education:
- Masters or foreign equivalent in Electrical Engineering or related field
Experience:
- 7 years of experience in job offered or related occupation.
Special Requirements: Must have at least 1 year of prior work experience in each of the following
Worksite:
- 6433 Champion Grandview Way Building 2 Suite 150 Austin Texas 78750
Applicant Instructions:
- Email resume to:
- Include job code 91498 in reply. EOE.
We may use artificial intelligence (AI) tools to support parts of the hiring process such as reviewing applications analyzing resumes or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed please contact us.
Required Experience:
Staff IC
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