FE Engineer
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Job Location:
Santa Clara County, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
30+ days ago
Vacancies:
1 Vacancy
Job Summary
* Building a test bench creating test vectors and running the verification environment to verify that the subsystem you designed works properly* Synthesize the subsystem into logic and perform Static Timing Analysis (STA) on the design to make sure it meets the timing requirements* Designing integrating and verifying a system fabric bus into a subsystem
- * Digital Logic Design knowledge
- * Verilog/System Verilog RTL language design entry
- * Synopsys/Cadence synthesis
- * Synopsys PrimeTime Static Timing Analysis (STA)
- * Synopsys (VCS)/Cadence(Incisive) simulation
- * Strong problem solving and analytical skills
- * Strong communication skills combined with team-oriented approaches to own the verification efforts in a specific area of the design
- * Experience/exposure writing specifications and documentation
- * Experience/exposure with verifying logic design hardware
- * Experience/exposure to front-end tools and methodologies
Key Skills
- ASP.NET
- Health Education
- Fashion Designing
- Fiber
- Investigation
About Company
Ask Siri to name the most successful company in the world and it might respond: Apple. And it's not just out of familial pride. Apple consistently ranks highly in profit, revenue, market capitalization, and consumer cachet. In 2018, the company became the first reach a trillion dollar ... View more
