SeniorStaff Physical Design Engineer

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the worlds most highly integrated SoCs Silicon Labs provides device makers the solutions support and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin Texas Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home industrial IoT and smart cities markets. Learn more at.

What were looking for:

We are seeking a highly skilled Design Engineer to join our Silicon Engineering team. This role involves driving the design implementation and optimization of cutting-edge SoCs through advanced physical design methodologies. The ideal candidate will have deep expertise in synthesis floorplanning place-and-route timing closure power/performance optimization and sign-off flows.

Skills youll need:

• Execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII).

• Define and drive floorplanning clock-tree synthesis (CTS) placement routing and timing closure strategies.

• Own and optimize power performance and area (PPA) metrics for assigned designs.

• Manage design constraints synthesis strategies and sign-off criteria (timing IR drop EM DRC/LVS).

• Collaborate with front-end RTL DFT verification and packaging teams to ensure seamless integration.

• Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability.

• Mentor and guide junior engineers fostering technical growth and design excellence.

• Work closely with foundries and vendors on process technology bring-up PDK updates and tape-out readiness.

Education and/or Experience:

• Bachelors or Masters degree in Electrical Engineering VLSI or related field.

• 4 years of experience in ASIC physical design

• Hands-on expertise in EDA tools: Synopsys (ICC2 Fusion Compiler PrimeTime)

• Cadence (Innovus Tempus) or equivalent.

• Strong background in timing analysis low-power methodologies and ECO

• flows.

• Solid understanding of architecture-to-GDSII flows and sign-off requirements.

• Experience with chip-level integration and hierarchical design methodologies.

• Knowledge of low-power design techniques (UPF/CPF power gating DVFS).

• Familiarity with DFT STA and physical verification methodologies.

• Exposure to multi-clock multi-voltage and multi-domain designs

• Excellent problem-solving and communication skills.

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Employee Stock Purchase Program (ESPP)

• Medical and dental insurance coverage including spouse and child(ren)

• Bi yearly health screening and flu vaccination

• Office location is above Tai Seng MRT station

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Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race religion color national origin gender sexual orientation age marital status veteran status or disability status or any other characteristic protected by applicable law.