Design Verification Principal Engineer
Design Verification Principal Engineer
Employer Active
Job Alert
You will be updated with latest job alerts via email
Share
Job Alert
You will be updated with latest job alerts via email
Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fastgrowing product lines Marvell technology is powering the nextgeneration data processing and workload acceleration platforms for the Carrier Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business Cloud AI solutions & Enterprise/Career solutions including the CXL product line.What You Can Expect
Job Responsibilities: SOC Sub system & Block verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys Specification to Silicon. Responsible for complete SOC/Subsys/Block verification activities like - develop verification architecture and verification plan develop UVM based testbench Integrate in-house verification components complex VIPs ( ARM Cadence Synopsys etc) develop test cases (UVM & assembly) verify and do coverage analysis in RTL and gate level design. Conduct reviews in all the SOC/Subsys verification phases to achieve desired quality on-schedule deliverables and drive SOC/Subsys verification process improvement. Mentor junior engineers and technically guide and monitor them on their day to day technical tasks. Work effectively with a global team and be self-motivated to manage deliverables Communicate clearly both verbally and in writing.What Were Looking For
Technical Requirements: Bachelors degree in CS/EE with 1418 years of relevant experience or Master degree in CS/EE with 1216 years of relevant experience Must Lead a team of 4-6 engineers Experience in SOC/Subsys level/Block verification of ARM-based SOCs; experience in ARM based boot environment preferred. Knowledgeable of ARM architecture and AMBA bus standards like AXI-4 CHI and ACE. Experience with industry standard interfaces such as DDR eMMC PCIE Ethernet and USB. Experience in coding UVM SOC/Subsys level testbenches BFM scoreboards monitors etc. Proficient in writing and debugging tests in UVM as well as C. Exposure to Cadence Synopsys Mentor and/or ARM verification tools. Experience with assertion-based formal verification tools. Proficient in programming in scripting languages such as tcl and Perl. Understanding of hardware emulation support. Familiarity with TLMs in SystemC. Experience in Version tools like CVS SVN GIT etc.Additional Compensation and Benefit Elements
With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Interview Integrity
As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.
#LI-CP1Required Experience:
Staff IC
Employment Type
Full-Time
