Principal Mixed Signal Design Engineer

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

As an Analog IC Design Principal Engineer with Marvell youll be a member of the Central Engineering business group. If you picture Marvell as a wheel Marvells Central Engineering organization provides the most advanced and key analog IPs to all businesses within Marvell: including Data Center Networking Automotive Storage Security. Youll be part of a key analog team that makes an outsized impact not only for the organization but also to the technological arc of innovation for future generations of Marvells high-speed wireline and optical products.

What You Can Expect

• Ownership of complex design blocks and complete analog macros.
• Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies with a focus on SerDes (Serializer/Deserializer) die-to-die communication and high-speed wireline design in general.
• Lead and contribute to the design of ADCs DACs Regulators Clock Generation and Distribution DLLs Custom high-speed digital circuits CTLE VGA and TX Drivers.
• Cooperate with system and architecture team in identifying the optimal circuit solution based on overall cost function
• Supervise coach and provide technical direction to more junior engineers
• Supervise and guide layout activities to ensure design accuracy and performance.
• Conduct post-silicon testing and validation of analog mixed-signal circuits.
• Collaborate with cross-functional teams to ensure successful project execution.
• Prepare and maintain detailed documentation of design processes and results.
• Participate and lead design reviews to ensure design quality and compliance with project requirements.

What Were Looking For

• MS/PhD in Electrical Engineering and 10 years of demonstrated experience in high-speed and low-power design on advanced CMOS technologies specifically in one or more of the following areas: ADC DAC voltage regulators clock generation and distribution circuits DLLs custom high-speed digital circuits CTLE VGA and TX drivers.
• Proven track record of successfully bringing multiple tape-outs to production.
• Ability to independently assess design trade-offs and select the best one based on business needs and implementation risk.
• Ability to identify analyze and resolve complex design challenges and issues ensuring robust and reliable circuit performance.
• Ability to technically coordinate the work of junior employees providing mentorship and guidance.
• Experience in overseeing layout engineers providing guidance on best practices and ensuring that layout designs meet performance area and reliability requirements.
• Proficiency in post-silicon validation including hands-on experience with lab equipment debugging and characterization of analog mixed-signal circuits.
• In-depth knowledge of CMOS process technology device physics and the impact of process variations on circuit performance.
• Proficient in using electronic design automation (EDA) tools for schematic capture simulation layout and verification such as Cadence Synopsys or Mentor Graphics.
• Very good understanding of related areas such as RTL Firmware Design Verification Design for Test and Physical Design.
• Strong communication and teamwork skills.

Expected Base Pay Range (USD)

165630 - 248100 $ per annum

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell we offer a total compensation package with a base bonus and and financial wellbeing are part of the package. That means flexible time off 401k plus a year-end shutdown floating holidays paid time off to volunteer. Have a question about our benefits packages - health or financial Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.

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