FE Engineer
FE Engineer
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
- * Digital Logic Design knowledge
- * Verilog/System Verilog RTL language design entry
- * Synopsys/Cadence synthesis
- * Synopsys PrimeTime Static Timing Analysis (STA)
- * Synopsys (VCS)/Cadence(Incisive) simulation
- * Strong problem solving and analytical skills
- * Strong communication skills combined with team-oriented approaches to own the verification efforts in a specific area of the design
- * Experience/exposure writing specifications and documentation
- * Experience/exposure with verifying logic design hardware
- * Experience/exposure to front-end tools and methodologies
Employment Type
Full-Time
