Verilog and SystemVerilog coding - HYDERABAD - WFO
Verilog and SystemVerilog coding - HYDERABAD - WFO
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Job Description
This role is primarily focused on digital design and verification with a strong emphasis on Verilog and SystemVerilog coding. The ideal candidate should have a solid background in RTL design and verification methodologies as well as practical experience with static checks and IP release processes.
Key Responsibilities:-
Develop and verify RTL designs using Verilog and SystemVerilog.
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Participate in the design and verification cycle from spec understanding to sign-off.
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Ensure code quality and consistency through the use of static analysis tools and methodologies.
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Collaborate with cross-functional teams to deliver high-quality IP for integration and release.
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Strong proficiency in Verilog and SystemVerilog (SV) coding.
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Solid background in digital design and functional verification.
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Hands-on experience with Lint CDC (Clock Domain Crossing) and VCLP static check flows.
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Familiarity with IP design development and managing quality IP releases.
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Experience in applying and maintaining static checks methodology for design consistency and quality.
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Understanding of industry-standard tools and scripting to automate static checks.
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Exposure to SoC or ASIC development environments.
Employment Type
Full-time
