Verilog and SystemVerilog coding - HYDERABAD - WFO

Trigent Software Private Limited

Job Location:

Hyderabad - India

Monthly Salary: Not Disclosed

Posted on: 30+ days ago

Vacancies: 1 Vacancy

Job Summary

Role & Detailed Understanding

This role is primarily focused on digital design and verification with a strong emphasis on Verilog and SystemVerilog coding. The ideal candidate should have a solid background in RTL design and verification methodologies as well as practical experience with static checks and IP release processes.

Key Responsibilities:

Develop and verify RTL designs using Verilog and SystemVerilog.
Participate in the design and verification cycle from spec understanding to sign-off.
Ensure code quality and consistency through the use of static analysis tools and methodologies.
Collaborate with cross-functional teams to deliver high-quality IP for integration and release.

Required Qualifications:

Strong proficiency in Verilog and SystemVerilog (SV) coding.
Solid background in digital design and functional verification.

Preferred Qualifications:

Hands-on experience with Lint CDC (Clock Domain Crossing) and VCLP static check flows.
Familiarity with IP design development and managing quality IP releases.
Experience in applying and maintaining static checks methodology for design consistency and quality.

Nice to Have:

Understanding of industry-standard tools and scripting to automate static checks.
Exposure to SoC or ASIC development environments.

Role & Detailed Understanding This role is primarily focused on digital design and verification with a strong emphasis on Verilog and SystemVerilog coding. The ideal candidate should have a solid background in RTL design and verification methodologies as well as practical experience with static chec...