Senior Technical Staff Engineer - Design (IO Lead Design-FPGA)
Senior Technical Staff Engineer - Design (IO Lead Design-FPGA)
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Job Description
Are you looking for a unique opportunity to be a part of something great Want to join a 17000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust empowerment respect diversity and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchips nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development values-based decision making and strong sense of community driven by our Vision Mission and 11 Guiding Values; we affectionately refer to it as the Aggregate System and its won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.
Visit our careers page to see what exciting opportunities and company perks await!
Job Description:
Microchip Technology Inc. has a Senior Technical Staff Engineer - IO Design Lead opening based in Chandler Arizona. This engineer will be responsible for providing technical leadership in the architecture definition design modeling integration and verification of complex analog circuitry (clocking Rx Tx) integrated into the IOs of the FPGA.
Develop analog circuits for GPIO HSIO high-speed DDR and other IO applications in advanced FinFET nodes.
Work with architecture team to understand chip requirements and translate them into circuit architectures and implement and simulate them.
Contribute to the micro architecture and circuit design simulation and optimization of various IO blocks such as clocking (PI DLL PLL) CTLE VGA Tx.
Collaborate with layout and ASIC PnR team to optimize IO floorplan placement and routing of power and critical signals.
Develop IO system models to determine system budgets identify performance bottlenecks and create implementable design specs.
Drive analog and digital design AMS verification layout across different geographies and time zones.
Improve current and develop new calibration and training algorithms of various sub-blocks in the IOs to meet high-speed performance.
Work with the ESD engineer to integrate the ESD design into IO blocks.
Layout guidance and mentorship of junior engineers.
Work with the layout lead in planning the distribution of critical signals and clocks placement of IO blocks and design of the IO power distribution network.
Propose new mixed-signal flows for IO designs that will enhance the efficiency and quality of current and future designs
Investigate new architectures and circuit design techniques for current and future generations of FPGA IOs.
Support IO Mixed-Signal IP through post-tapeout phase including lab testing customer bring-up and debug.
Requirements/Qualifications:
Bachelors and/or Masters in Electrical Engineering Physics Computer Engineering or Computer Science preferred.
15 years of proven silicon experience in design and verification of high-speed IOs and verification efforts in multiple technology nodes.
System modeling of IOs using Matlab and System C/System Verilog.
Familiarity with FinFet technology. Knowledge go industry standard tools like Spice Virtuoso AMS/Co-sim Matlab.
Competency in HSPICE co-sim and testbench generation and simulation.
Knowledge about high speed design techniques (DDRx PCI-e USB MIPI) and calibrations.
Demonstrated competency in scripting managing simulation queues and data capture plus presentation using Microsoft Office tools including Excel.
Knowledge of power analysis.
Good analytical oral and written communication skills
Able to write clean readable presentations.
Self-motivated proactive team player.
Ability to work to schedule requirements.
Travel Time:
0% - 25%Physical Attributes:
Feeling Handling Hearing Seeing Talking Works Alone Works Around OthersPhysical Requirements:
15% standing 15% walking 70% sitting; 100% In doors; Usual business hoursMicrochip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex gender identity sexual orientation race color religion national origin disability protected Veteran status age or any other characteristic protected by law.
For more information on applicable equal employment regulations please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.
To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
Required Experience:
Staff IC
Employment Type
Full-Time
