PSV NPU Validation Engineer
PSV NPU Validation Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
Location: San JoseCA
- Develop end-to-end system validation test plans for the NPU including characterization.
- Collaborate with cross-functional teams including software and hardware engineers to design optimal test validation and characterization solutions.
- Create modify and refine tests based on a deep understanding of the NPU design ensuring comprehensive coverage and suggesting improvements where necessary.
- Lead the development and execution of bring-up validation qualification tuning and productization plans.
- Build and integrate necessary tools scripts and infrastructure in close collaboration with stakeholders.
- Spearhead post-silicon bring-up efforts and provide expert support for debugging activities.
- Drive continuous optimization of validation and productization methodologies to improve overall process efficiency and quality.
- Minimum 6 years of experience in validating and debugging complex systems.
- In-depth knowledge of computing architecture technical debugging and validation strategies.
- Hands-on experience with silicon bring-up debugging and characterization of SoC-level IPs (e.g. PCIe Gen 4/5 LPDDR4/5 PLL/DLL NOR Flash SPI I2C RISC-V processors) with familiarity in memory and I/O interfaces.
- Strong debugging skills with the ability to analyze complex issues using first principles.
- Experience with Lauterbach Debugger for RISC-V and lab equipment (oscilloscopes BERT power supplies logic analyzers) is strongly preferred
- Solid foundation in digital design microarchitecture timing power noise control systems and HW/SW interaction including firmware.
- Proficiency in programming/scripting (C/C Perl Ruby Python) for automation test scripting and GUI development. Knowledge of signal and power integrity is a plus.
Employment Type
Full-time
