Graphics FE Implementation Engineer
Graphics FE Implementation Engineer
Posted on :
03-08-2025
Employer Active
1 Vacancy
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Monthly Salary
USD 126800 - 190900
Vacancy
1 Vacancy
Posted on :
03-08-2025
Job Description
Candidates will be responsible for RTL to netlist generation working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition engage in Lint CDC Logic equivalence checks and support ECO generation activities. Through this collaboration you will deliver the best-in-class GPUs for the best consumer products. If youre ready to help chart the future of Apple Silicon wed love to talk to you.
- Relevant Coursework in Computer Architecture Digital Logic Design and CMOS VLSI design
- Experience with at least one scripting language (python/perl/tcl)
- BS required
- Familiarity with Verilog and System Verilog
- Exposure to industry standard rtl2gds tools for synthesis place and route static timing analysis
- Exposure to Clock/Reset domain crossing or Voltage crossing principles
- Familiarity with DFT methodologies
- Knowledge of static timing analysis concepts (setup and hold timing)
- Understanding of CMOS device characteristics for area/timing/power tradeoffs
Employment Type
Full Time
Key Skills
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