Physical Design Lead â Custom Silicon Management
Physical Design Lead â Custom Silicon Management
Posted on :
02-08-2025
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1 Vacancy
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Monthly Salary
USD 172100 - 305600
Vacancy
1 Vacancy
Posted on :
02-08-2025
Job Description
You will have the opportunity to integrate and come-up with new insights as well as work with vendors to promote efficiency in the Silicon value your technical understanding of physical design principles. You will be responsible for ensuring the high quality of the chips and is expected to:Audit vendor PD flows and methodologies for any holes and set up improvements to their methodology to optimize it to obtain the best QoR for Apple closely with the internal teams like systems and program management to ensure that the vendor PD implementation team is meeting the design closely with specialists from other teams like the packaging process etc. to resolve any issues in the project which are in an area closely related to periodic design reviews - with deep technical dives - to make sure the project is tracking to the schedule and maintaining a high quality of all the final PD STA SI Electrical analysis reports and sign-off on them for tapeout post tapeout support to work on ECOs and debug if to a strict and consistent standard of operation across all vendors and a professional relationship with the vendor and yet walk the fine line to maintain the customer-vendor distance.
- BS and 10 years of experience in Physical Design.
- Knowledge of digital design concepts.
- Experience leading physical design teams.
- Track record of having taped out a number of complex chips - from gates to GDS.
- Working knowledge of front-end design methodology including basic RTL coding synthesis methodology timing constraints generation multiple clock domain handling low power techniques.
- In depth practical hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning ESD techniques floor planning power planning clock tree synthesis MCMM timing closure routing DFM techniques and physical verification.
- Working knowledge of at least one of the industry CAD tools - Cadence Synopsys Mentor or Atoptech.
- Proficient in Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing.
- Hands-on experience in Power and Signal Integrity analysis.
- Ability to debug and fix LVS DRC Antenna ERC issues.
- Familiarity with the best analog layout design practices for sensitive circuits like OpAmp matching pair etc.
- Mixed signal SoC tapeouts involving multiple instances of analog IPs.
- Low power / leakage management methodology and techniques.
- Extraction and characterization of IP elements.
Employment Type
Full Time
Key Skills
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