RTL Design Engineer
RTL Design Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
- BS degree in technical discipline with minimum 10 years of relevant experience.
- Deep knowledge of mixed signal concepts
- Deep knowledge of RTL design fundamentals
- Deep knowledge of Verilog and System-Verilog
- Deep knowledge of front-end tools (Verilog simulators linters clock-domain crossing checkers)
- Working knowledge of synthesis static timing DFT is a huge plus
- Deep knowledge of System-Verilog assertions checkers and other design verification techniques
- Deep knowledge of scripting languages. Perl and Python are plusses
- Deep knowledge of Algorithm developments
- Strong communication and presentation skills SERDES knowledge is a plus
Employment Type
Full Time
