ASIC Emulation Engineer (Hybrid)
ASIC Emulation Engineer (Hybrid)
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Job Description
Seeking a skilled ASIC Emulation Engineer with a strong background in System-on-Chip (SoC) design.
You will be responsible for developing and executing emulation strategies for complex ASIC designs enabling early hardware/software co-development and system validation.
You will work closely with RTL designers verification engineers and software teams to ensure the functionality and performance of the SoC.
The ideal candidate should have experience with FPGA-based emulation platforms strong debugging skills and a deep understanding of SoC architecture and interfaces.
Key Responsibilities:
Develop and implement ASIC emulation plans for SoC designs.
Collaborate with cross-functional teams to validate hardware and software integration.
Debug and resolve issues in the emulation environment.
Optimize emulation performance and coverage.
Provide feedback to design and verification teams to improve design quality.
Required Skills
Experience with FPGA-based emulation platforms (e.g. Synopsys Cadence).
Strong knowledge of SoC architecture RTL design and verification.
Proficiency in Verilog/SystemVerilog and scripting languages.
Experience with Universal Verification Methodology (UVM).
Knowledge of Constraint Driven Verification (CDV) techniques and assertion-based verification.
Familiarity with Verilog and SystemVerilog assertions.
Qualifications:
Bachelors or Masters degree in Electrical Engineering Computer Engineering or a related field.
Employment Type
Full-time
