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You will be updated with latest job alerts via emailResponsibilities :
Design and lead high speed IP (USB3 PCIE DPHY etc) development. Need to be a strong individual contributor in analog domain. Will be required to participate in all aspects of development analog design layout digital design documentation and silicon validation. Would be required to participate in customer facing discussions.
Requirements
- 4 yrs
Hands on design experience in various analog IP like PLLs data converters serial interfaces etc.
Must have participated in full cycles of analog IP creation right from spec to silicon debug and char
Must have good communication skills and should be team player.
Working experience in PHY (PCIE USB2 USB3) development is desired
Full-Time