Key Responsibilities:
- SRAM Layout Design: Design and implement memory layout for SRAM cells arrays and associated circuitry using industry-standard EDA tools (e.g. Cadence Synopsys).
- Cell Optimization: Work on optimizing SRAM cells for performance power and area (PPA) trade-offs while adhering to design rules.
- DRC/LVS: Perform Design Rule Checks (DRC) and Layout Versus Schematic (LVS) verification to ensure layout correctness.
- Process Technology: Adapt the SRAM layout design to different semiconductor process nodes and technologies (e.g. 7nm 14nm etc..
- Power and Area Optimization: Optimize SRAM design for power consumption and die area while ensuring robust functionality.
- Test and Validation: Collaborate with simulation teams for physical verification and test design ensuring layout integrity and compliance with functional requirements.
- Collaboration: Work closely with circuit designers CAD engineers and other stakeholders to ensure seamless integration of SRAM layouts into larger system-on-chip (SoC) designs.
- Documentation: Provide detailed documentation for layout design analysis and verification processes.
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