Design Verification Engineer - Data Fabric Systems
Design Verification Engineer - Data Fabric Systems
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Job Description
Project Description:
We are passionate about transforming lives through cuttingedge technology enriching industries communities and the world. Our mission is to create exceptional products that drive nextgeneration computing experiences serving as the foundation for data centers artificial intelligence PCs gaming and embedded systems.
At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the worlds most critical problems. We are committed to execution excellence fostering a culture of openness humility collaboration and inclusivity valuing diverse perspectives along the way. As Design Verification Engineer you will join leadingedge team responsible for the verification of advanced interconnect systems in stateoftheart microprocessors. This role focuses on ensuring the functionality performance and reliability of highbandwidth data communication architectures.
We are looking for someone who has a passion for modern complex processor architecture digital design and verification in general. Who are a team player and has good communication skills strong analytical and problemsolving skills and willing to learn and ready to accept challenges.
Skills required:
- Proficiency in SystemVerilog and UVM
- 5 years of relevant experience
- Experience with formal verification techniques
- Strong understanding of digital design and verification processes
- Knowledge of interconnect or fabric architectures
- Experience working in a Unix/Linux environment
Nice To Have:
- Familiarity with performance modeling
- Background in Verilog and digital design
- Experience with highbandwidth interconnect protocols
Responsibilities:
- Perform preSilicon Verification of next generation high performance Microprocessor designs and related IPs
- Develop document and execute on verification test plans at unit level of design hierarchy
- Develop high level language testbench components including stimulus drivers behavioral models monitors and checkers in SystemVerilog
- Develop simulate and debug directed/random stimulus to ensure design functionality according to specifications
Employment Type
Full Time
