Sr Principal Design Engineer
Sr Principal Design Engineer
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Job Description
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software hardware and IP that turn design concepts into reality.
Cadence customers are the worlds most innovative companies delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer hyperscale computing 5G communications automotive aerospace industrial and health.
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Sr Principal Design Engineer
Location: Poland
Reports to: Design Engineering Director
Job Overview:
The Cadence IP Group (IPG) develop leading edge Intellectual Property (IP) for a variety of HighTech Markets. The Cadence IP solutions allow our Customers to tackle IPtoSoC development in a system context enabling them to focus on product differentiation and to reduce time to volume.
The Cadence IP Vision is to deliver industryleading IP solutions that enable our customers to succeed in these fastmoving application spaces.
The Sr Principal Design Engineer will be based in Katowice Poland as part of an experienced Controller IP Team with long established Controller development sites in Europe and India.
Experience: 12 years
Job Responsibilities:
- Development of complex IP such as PCIe UCIe CXL Ethernet MIPIVisual
- Development of RTL Testbenches & FPGA Platforms
- Technically leads small teams/multidiscipline
- Deployment of Frontend design tools e.g. LINT Synthesis and CDC Tools
- Support customer presales and postsales meetings
- Participate in Technical Review Meetings and Checklist Reviews as part of ISO9001
- Represent Cadence in Standards Body Working Groups e.g. JEDEC IEEE PCISIG MIPI
Job Qualifications:
- Degree in Electrical/Electronic Engineering Microelectronics or a related discipline
- 12 years experience in microelectronics/EDA industry
- Proficient in Verilog coding RTL design and complex control path and data path designs
- Knowledge of any of the interface Protocols like ONFi UCIe PCIe USB MIPI Ethernet
- Experience of Metric Driven Verification (MDV) essential
- Knowledge of RTL checks LINT SDC CDC
- Familiar with synthesis flow LEC and timing constraints
- Experience in writing Verilog testbench and running simulations
- Excellent oral and written English essential
- Selfmotivated with excellent planning interpersonal and communication skills
Additional Skills/Preferences:
- Experience of AMBA PCIe CXL & UCIe protocols preferred
- Experience of Quality processes such as ISO9001 & ISO26262 preferred
Additional Information:
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
Check out what we can offer you:
- Private Health Insurance
- 5 days Volunteering Time off each year
- Employee Stock Purchase Plan
- Competitive salary package adequate to competencies
- Internet Expenses reimbursement
- Competitive Referral Program
- Work from the office or Hybrid Work
- Flexible working hours
- Life insurance
- Multisport Plus cards
- Social Fund benefits
- Recommendation bonuses & Internal recognition program
Were doing work that matters. Help us solve what others cant.
Required Experience:
Staff IC
Employment Type
Full-Time
